Flip-Flop Gray Counter for Fast Low-DNL Image Sensor ADCs

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing image sensors face challenges in converting analog light signals into digital signals efficiently due to delays and differential non-linearity caused by logic gates and replica circuits in the analog-to-digital conversion process.

Innovation Solution

The implementation of a gray counter using flip-flops to generate gray code signals in synchronization with a clock signal, which avoids delays and differential non-linearity by removing the need for logic gates and replica circuits, allowing for high-speed image sensing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If logic gates and replica circuits are used in the analog-to-digital conversion process, then the conversion can be performed, but delays and differential non-linearity occur

Engineering Contradiction:
Improveconversion precisionVSAvoidconversion delay
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent extracts and removes the logic gates and replica circuits from the analog-to-digital conversion process. By eliminating these problematic components, the invention avoids the delays and differential non-linearity they cause, while maintaining conversion functionality through an alternative gray code generation approach using simple flip-flops.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses multiple flip-flops to generate gray code signals by copying and delaying clock signals through simple sequential logic. This copying mechanism creates the necessary gray code sequences without requiring complex logic gates, thereby achieving conversion functionality with minimal delay and non-linearity.

Inventive Principle:
Principle #26Copying

2Productivity

If logic gates and replica circuits are used in the analog-to-digital conversion process, then the conversion can be performed, but differential non-linearity occurs

Engineering Contradiction:
Improveconversion speedVSAvoiddifferential non-linearity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent removes the replica circuits that cause differential non-linearity from the conversion system. By replacing them with a gray code generation circuit based on flip-flops, the invention maintains high conversion speed while eliminating the source of differential non-linearity errors.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the fundamental approach from using analog replica circuits to using digital flip-flop-based gray code generation. This parameter change from analog to digital implementation eliminates differential non-linearity while preserving or improving conversion speed through simpler, more reliable digital logic.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If traditional counter technologies are used, then the analog-to-digital conversion can be implemented, but delays and differential non-linearity are introduced

Engineering Contradiction:
Improveconversion reliabilityVSAvoidsignal delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements a gray code generation circuit that copies and delays clock signals through a series of flip-flops to generate the required gray code sequences. This copying approach provides reliable signal generation without the delays associated with traditional counter technologies, as each flip-flop simply replicates and phases the clock signal.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS11317047B2Gray counter and image sensor including the same
Publication Date: 2022.04.26 SAMSUNG ELECTRONICS CO LTD
  • US11317047B2 patent drawing
  • US11317047B2 patent drawing
  • US11317047B2 patent drawing

AI summary

An image sensor includes a pixel sensor that senses an incident light and outputs a sampling signal of an analog shape, a sampler that compares the sampling signal and a ramp signal and outputs a comparison signal being time-axis length information, and a gray counter that counts a length of the comparison signal in synchronization with a clock signal and outputs a digital value. The gray counter includes a first flip-flop that divides the clock signal by 2 and generates a first gray code signal, a second flip-flop that delays a first data signal being a four-divided signal of the clock signal and outputs a second gray code signal, and a third flip-flop that delays the second gray code signal being two-divided and outputs a third gray code signal.