Gated Flip-Flop Clocking for Lower Toggle Power
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Solution Overview
Problem
Flip-flops in integrated circuits consume significant power, especially when numerous, which is undesirable in mobile applications where reducing active power consumption is crucial.
Innovation Solution
A flip-flop device with a gating circuit that generates lower-activity clock signals (clk_nand and clk_nor) from a full-activity input clock signal (CP), reducing signal transitions and thereby lowering power consumption, by using a selecting circuit, master circuit, slave writing circuit, and slave circuit configured to operate during writing and storing modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full-activity clock signal is used to control the flip-flop, then the flip-flop operates reliably, but the power consumption increases
Solution Approach 1:
The patent segments the single full-activity clock signal into two separate half-activity clock signals (clk_nand and clk_nor). Each clock signal operates at half the activity level of the original clock, controlling different portions of the flip-flop circuitry. This segmentation reduces the total number of signal transitions while maintaining functional reliability through the master-slave architecture.
Solution Approach 2:
The patent dynamically adjusts clock signal activity levels based on operational requirements. The gating circuit generates clock signals whose activity level adapts to the current operating mode (testing vs. normal operation), allowing the system to optimize power consumption while maintaining reliability when needed.
2Adaptability or versatility
If numerous flip-flops are applied in an integrated circuit, then the functionality and state storage capacity increase, but the total power consumption dominates the integrated circuit
Solution Approach 1:
The patent implements periodic action through the master-slave flip-flop architecture where clock signals are generated periodically at half-activity levels. The gating circuit produces clock signals that alternate between active and inactive phases, reducing the frequency of transitions. This periodic operation allows numerous flip-flops to be used for increased state storage capacity while significantly reducing the cumulative power consumption of the integrated circuit.
3Loss of energy
If the toggle rate of clock signals is reduced, then the power consumption decreases, but the operation speed may be affected
Solution Approach 1:
The gating circuit acts as an intermediary between the input clock signal and the internal clock signals (clk_nand and clk_nor). It transforms the full-activity input clock into two half-activity clock signals that maintain the necessary timing relationships. This intermediary function allows the system to operate at reduced clock activity levels without compromising the speed and timing requirements of the flip-flop operation.
Data Source
AI summary
An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.