Flip-Flop Input Freezing for Low-Leakage Data Retention
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Solution Overview
Problem
Existing flip flop-based circuits face challenges in reducing current consumption during Data Retention Mode while preserving data integrity, as conventional methods either increase complexity and time or incur significant area and cost due to additional low leakage latches.
Innovation Solution
A device with a flip flop and control circuit that applies fixed signal values to the flip flop input terminals during Data Retention Mode, independent of incoming data and clock signals, allowing driver circuits to be deactivated without generating leakage currents, thus reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data contents are transferred to other storage circuits (integrated register files or SRAM) before changing to Data Retention Mode, then current consumption is reduced, but device complexity and implementation time increase significantly
Solution Approach 1:
The patent extracts the data retention function from external storage circuits and implements it within the flip-flop itself using a specialized retention circuit. This eliminates the need for separate SRAM or register files, thereby reducing device complexity while maintaining low current consumption during retention mode.
Solution Approach 2:
The patent combines the data storage and retention functions into a single integrated flip-flop structure. The retention circuit is merged with the flip-flop logic, allowing data to be held within the same device without requiring external storage circuits, thus reducing overall system complexity.
2Loss of energy
If additional low leakage latch (LLL) is added per bit for Data Retention Mode, then leakage current is reduced, but area and cost increase significantly
Solution Approach 1:
The patent merges the low leakage latch functionality directly into the flip-flop structure, sharing circuit elements and logic. This integration allows the retention function to be achieved without adding separate LLL circuits for each bit, thereby reducing the overall area while maintaining low leakage current characteristics.
Solution Approach 2:
The patent designs a multi-functional flip-flop circuit that performs both normal data storage and low-leakage retention operations using a unified structure. The same circuit elements serve multiple purposes depending on the operational mode, eliminating the need for dedicated retention-only hardware and reducing total area.
3Use of energy by moving object
If flip flop is decoupled from supply voltage in Data Retention Mode, then current consumption is reduced, but data must be transferred to and from additional storage circuits
Solution Approach 1:
The patent extracts the retention functionality from external storage circuits and embeds it within the flip-flop itself. This allows the flip-flop to be decoupled from the supply voltage during retention mode while maintaining data internally, eliminating the need for complex data transfer operations to and from external storage.
Solution Approach 2:
The patent introduces a retention circuit as an intermediary structure within the flip-flop that can hold data in a low-power state. This intermediary structure enables the flip-flop to be decoupled from the supply voltage while preserving data, without requiring external storage circuits or complex data transfer mechanisms.
Data Source
AI summary
A device includes a flip flop and a control circuit. The flip flop includes a flip flop data input terminal and a flip flop clock input terminal. The control circuit includes a control circuit data input terminal and a control circuit clock input terminal. The control circuit is configured to route, in a Data Processing Mode of the device, an incoming data signal from the control circuit data input terminal to the flip flop data input terminal and an incoming clock signal from the control circuit clock input terminal to the flip flop clock input terminal and to apply, in a Data Retention Mode of the device, a first given fixed signal value to the flip flop data input terminal independent of a value of the incoming data signal and a second given fixed signal value to the flip flop clock input terminal independent of a value of the incoming clock signal.