Flip-Flop Insertion Optimization for Semiconductor Circuit Design
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Solution Overview
Problem
Existing semiconductor integrated circuit design technologies face inefficiencies in optimizing the placement of flip-flops (FFs) during high-level synthesis, leading to suboptimal circuit scale and processing performance due to non-ideal FF insertion positions.
Innovation Solution
A semiconductor integrated circuit design supporting apparatus that calculates necessary delays, extracts input FF stages, and optimizes FF insertion positions to minimize the total number of FFs, allowing for re-adjustment of latency and subsequent high-level synthesis to achieve a smaller circuit scale.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If FFs are automatically inserted between modules to adjust latency, then latency adjustment is achieved, but circuit scale increases due to non-optimal FF placement
Solution Approach 1:
The patent performs preliminary analysis of module internal FF stages before inserting FFs between modules. By extracting and analyzing the FF stage information within each module in advance, the system identifies optimal insertion points that account for existing internal FFs, preventing redundant insertions and minimizing overall circuit scale while achieving the required latency adjustment.
Solution Approach 2:
The patent applies different treatment to different locations by analyzing the specific FF stage configuration of each module individually. Instead of uniformly inserting FFs between all modules, the system evaluates each module's internal FF structure and determines the optimal number and position of inter-module FF insertions based on local characteristics, thereby reducing unnecessary FFs and circuit complexity.
2Loss of time
If FFs are inserted between modules for latency adjustment, then processing latency is reduced, but processing speed decreases due to increased circuit scale
Solution Approach 1:
The system performs preliminary extraction and analysis of FF stage information within modules before conducting latency adjustment. This advance preparation enables identification of optimal FF insertion positions that minimize the total number of FFs, thereby reducing circuit scale and preventing degradation of processing speed while still achieving the required latency adjustment.
Solution Approach 2:
The patent optimizes the parameters of FF insertion by dynamically determining the number of FFs to insert at each interface based on the internal FF stage configuration of connected modules. By adjusting the insertion count parameter according to actual module characteristics rather than using fixed rules, the system achieves latency adjustment with minimal impact on processing speed.
Data Source
AI summary
A latency adjusting part calculates a necessary delay based on the number of FFs that are required to be inserted between respective modules through high level synthesis of a behavioral description. An input FF stage number acquiring part extracts a pin having an input that receives an FF, and acquires the number of stages of input FFs of FF reception. A latency re-adjusting part obtains an optimum delay based on the above-mentioned necessary delay and input delay. A former-stage module analyzing part detects, based on the above-mentioned synthetic log or HDL, a state having a minimum total number of FFs. An FF insertion optimizing synthesis part subjects an entire circuit to high level synthesis again based on the above-mentioned optimum delay and an FF inserting position obtained based on the state having the minimum number of FFs, to thereby obtain optimized HDL.