Flip-Flop Inversion Error Detection in Logic Equivalence Check
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Solution Overview
Problem
In VLSI circuit design, the insertion of flip-flops to meet timing constraints often results in discrepancies between RTL and physical designs, leading to prolonged RTL-to-layout convergence time and false logic equivalence errors due to the limitations of conventional combinational equivalence check tools.
Innovation Solution
A computer-implemented method for automatic flip-flop insertion in integrated circuit design, using RTL-estimated count limits and timing analysis to determine necessary flip-flop placements, and employing a logic equivalence check tool to verify accuracy across flip-flop boundaries, thereby reducing the need for physical routing or logic design modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional combinational equivalence check tools are used to verify equivalence between RTL and gate-level designs, then the checking process is efficient and scalable, but false inversion errors occur due to inability to comprehend logic across flip-flop boundaries
Solution Approach 1:
The patent introduces an intermediary processing step that transforms the gate-level netlist by replacing flip-flops with their characteristic equations and simplifying the logic. This intermediary representation enables the conventional combinational equivalence check tool to accurately verify logic across flip-flop boundaries without sacrificing checking efficiency, thereby resolving the contradiction between productivity and reliability in equivalence checking
Solution Approach 2:
The patent changes the parameter representation of flip-flops by substituting them with their characteristic equations (next-state logic) and transforming the netlist into a form where sequential logic is expressed as combinational logic with explicit state variables. This parameter transformation allows conventional tools to handle sequential equivalence checking accurately while maintaining their efficiency advantages
2Loss of time
If RTL-estimated flip-flop insertion counts are used to guide physical design, then the initial placement and routing can be established quickly, but discrepancies between RTL and physical designs occur leading to prolonged convergence time
Solution Approach 1:
The patent implements a feedback mechanism where the physical design tool counts the actual flip-flops inserted in the gate-level netlist and compares this count with the RTL-estimated count. Based on this comparison, the tool provides feedback to adjust the physical design (placement or routing) to achieve the target flip-flop count, thereby reducing discrepancies and improving RTL-to-layout convergence while maintaining manufacturing precision
Solution Approach 2:
The patent performs preliminary flip-flop insertion based on RTL estimates before detailed placement and routing, establishing an initial physical design structure. This preliminary action allows quick establishment of the design framework, and subsequent feedback-driven adjustments refine the flip-flop count accuracy without significantly increasing overall convergence time
Data Source
AI summary
System and method of checking logic equivalence following flip-flop insertions to identify paths with inversion errors. All the flip-flops in a gate-level netlist and the corresponding RTL design are treated as buffers in a logic equivalence check (LEC) tool. A logic mismatch of a path between the RTL design and the netlist indicates an odd number of inverters have been inserted in the path during a flip-flop insertion process. Accordingly, the identified path is adjusted to ensure an even number of inverters.