Semi-Dynamic Flip-Flop Keeper Gating for Faster Evaluation
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Solution Overview
Problem
Semi-dynamic flip-flop circuits in high-performance computing systems face challenges in achieving faster performance and stability due to the inherent 'fight' between the dynamic node and the keeper circuit during the transition from pre-charge to evaluation phase, leading to delays in operation.
Innovation Solution
Incorporating a PMOS keeper control device with a three gate delay self-timed positive pulse to control the keeper circuit, which actively turns on and off the PMOS transistor, reducing the conflict between the dynamic node and the keeper circuit, thereby increasing the data to output delay and enhancing microprocessor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a keeper circuit is used to hold the state of the flip-flop stable, then stability is improved, but the fight between the discharge of the dynamic node and the keeper circuit increases the data to output delay
Solution Approach 1:
The patent applies the dynamics principle by making the keeper circuit dynamically controllable through a PMOS control device. The keeper circuit transitions from a static always-on state to a dynamic state where it can be selectively enabled or disabled based on the evaluation phase, resolving the conflict between maintaining stability and reducing delay.
Solution Approach 2:
The patent implements preliminary action by pre-charging the dynamic node to a logic high state before the evaluation phase begins. This pre-charging action, controlled by the PMOS device, ensures the node is ready for evaluation without requiring the keeper circuit to actively maintain the state during the entire pre-charge period, thereby reducing unnecessary conflict and delay.
2Reliability
If the keeper circuit is always active to maintain the precharge state, then stability is improved, but the area consumed by the circuit increases
Solution Approach 1:
The PMOS control device enables dynamic control of the keeper circuit, allowing it to be activated only when needed during the evaluation phase. This dynamic approach replaces the need for always-active keeper circuits with multiple redundant circuits, thereby reducing the total area consumed while maintaining stability during critical operations.
3Speed
If the evaluation window is fully open to allow data evaluation, then speed is improved, but noise susceptibility increases
Solution Approach 1:
The patent applies local quality by creating a partially floating evaluation window where the dynamic node is isolated from noise sources during specific sub-intervals of the evaluation phase. The PMOS control device enables selective connection to VDD during different portions of the evaluation window, providing local protection against noise while maintaining overall evaluation speed.
Data Source
AI summary
Implementations of the present disclosure involve a semi-dynamic flip-flop circuit incorporating a partially floating evaluation window that provides a faster data to output delay, a PMOS keeper device may be placed in series with an existing keeper circuit of the semi-dynamic flip-flop circuit. The gate of the PMOS series keeper device may be connected to a shut-off signal of the semi-dynamic flip-flop circuit that provides a three gate delay, self-timed positive pulse to control the keeper circuit. The PMOS series keeper device effectively turns off the keeper circuit when the clock signal rises but turns in back on after a three gate delay to sustain the precharge state of the dynamic node. The effective turning on and off of the keeper circuit portion may decrease the data to output delay of the flip-flop, resulting in higher performing microprocessors.