Flip-Flop Latch Reset for Constant Switching Current
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Solution Overview
Problem
Conventional flip-flops in synchronous systems generate pattern-dependent switching currents, which contaminate analog signals and compromise the security of devices like smart cards by revealing secret keys through differential power analysis.
Innovation Solution
A flip-flop design that includes an amplifier, a latch, and a control signal generator, where the latch is reset to zero at the beginning of each clock cycle using control signals generated by the control signal generator, eliminating the need for logic gates that introduce delays and thus minimizing pattern-dependent switching currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional static CMOS logic is used to implement flip-flops, then the device complexity is reduced and ease of manufacture is improved, but pattern dependent switching current is generated that contaminates analog signals and compromises security
Solution Approach 1:
The harmful pattern dependent switching current is extracted and eliminated by using a differential pair configuration where the total current remains constant. The invention separates the switching function from the current consumption pattern, allowing the flip-flop to change state without generating variable current draws that reveal information or contaminate analog signals.
Solution Approach 2:
The invention changes the current parameter from variable (pattern dependent) to constant by using a differential pair with a constant current source. This parameter transformation ensures that regardless of the data pattern being processed, the total current consumption remains fixed, eliminating the security vulnerability and analog signal contamination.
2Device complexity
If logic gates are used to generate control signals for latch reset, then the device complexity is reduced, but signal delay is introduced that prevents immediate reset at the beginning of each clock cycle
Solution Approach 1:
The invention introduces a direct control path from the clock signal to the latch reset mechanism, eliminating the need for intermediate logic gates. This intermediary-free path ensures that the latch is reset immediately at the beginning of each clock cycle without the time delays that would otherwise be introduced by gate propagation.
Solution Approach 2:
The latch is reset preliminarily at the very beginning of each clock cycle before any processing occurs. This preliminary reset action ensures that the latch is always in a known state at the start of each cycle, eliminating the need for complex control logic while maintaining precise timing control.
3Object-generated harmful factors
If the latch is reset immediately at the beginning of each clock cycle, then pattern dependent switching current is eliminated, but the control signal generation becomes more complex
Solution Approach 1:
The invention merges the clock signal function with the latch reset control function. By using the clock signal itself (or a direct derivative) to control the latch reset, the design eliminates the need for separate control signal generation logic. This merging approach achieves immediate reset timing while avoiding the complexity of additional control circuits.
Solution Approach 2:
The clock signal serves multiple functions: it provides the timing reference for the flip-flop operation and simultaneously controls the latch reset. This multi-functionality reduces the need for dedicated control signal generation circuits, achieving immediate reset without increasing overall device complexity.
Data Source
AI summary
A constant switching current flip-flop includes a latch circuit that provides latch outputs of the flip-flop, whereby the latch outputs are reset to zero at the beginning of each clock cycle to eliminate pattern dependent switching currents. The latch circuit is reset responsive to control signals provided without significant delay.