Flip-Flop Latch Timing for Stable Low-Voltage Operation

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Solution Overview

Problem

There is a limitation in lowering the operating voltage of semiconductor devices due to the risk of abnormal operations when the difference between the operating voltage and the threshold voltage of circuit elements is small.

Innovation Solution

The semiconductor device includes a flip-flop with a first and second latch, each having a data path and a feedback path. The feedback paths are disabled prior to enabling the data paths, and a clock buffer generates inverse and delay clock signals to control the flip-flop's operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the operating voltage is lowered to reduce power consumption, then power consumption is reduced, but abnormal operations occur when the difference between operating voltage and threshold voltage is small

Engineering Contradiction:
Improvepower consumptionVSAvoidoperation stability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The feedback path is disabled in advance before the data path is enabled. Specifically, the feedback transistor is turned off before the transmission gate is turned on, preventing simultaneous conduction and avoiding abnormal operations such as shoot-through current. This preliminary action allows the circuit to operate reliably at low voltages where simultaneous switching would cause instability.

Inventive Principle:
Principle #10Preliminary action

2Speed

If the feedback path and data path switch simultaneously, then circuit operation speed is maintained, but abnormal operations occur due to simultaneous conduction

Engineering Contradiction:
Improvecircuit operation speedVSAvoidoperation stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The feedback path is disabled in advance before the data path is enabled. The feedback transistor is turned off before the transmission gate turns on, creating a time sequence that prevents simultaneous conduction. This resolves the abnormal operations while maintaining efficient circuit operation through proper timing control.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The circuit uses dynamic timing control where the feedback path disable time and data path enable time are separated. By making the switching时序 dynamic and sequential rather than simultaneous, the circuit avoids shoot-through current while maintaining fast operation through optimized timing.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12224751B2Semiconductor device and semiconductor system having the same
Publication Date: 2025.02.11 SAMSUNG ELECTRONICS CO LTD
  • US12224751B2 patent drawing
  • US12224751B2 patent drawing
  • US12224751B2 patent drawing

AI summary

Disclosed is a semiconductor device which includes at least one flip-flop. The flip-flop includes a first latch that includes a first data path receiving input data in response to a transmission signal and outputting middle data, and a first feedback path feeding back the middle data, and a second latch that includes a second data path receiving the middle data in response to the transmission signal and outputting output data, and a second feedback path feeding back the output data, and at least one of the first feedback path and the second feedback path is disabled prior to the first data path or the second data path.