Specialized Flip-Flop Library for High Frequency ASIC Timing

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Solution Overview

Problem

Current semiconductor circuit designs fail to fully optimize circuit components for specific uses due to blanket optimizations, leading to inefficiencies in modern complex electrical circuits.

Innovation Solution

A method and system that perform timing analysis on electronic circuits to determine specialized storage elements adapted to specific operational attributes, such as setup times, hold times, and clock-to-output times, optimizing storage elements for specific edges of signals to improve circuit timing and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If standard storage elements are optimized for overall efficiency with multiple variables, then general circuit functionality is maintained, but specific path timing optimizations are lost

Engineering Contradiction:
Improvestorage element optimization for specific path attributesVSAvoidcircuit component optimization complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments storage element optimization into multiple specialized versions, each tailored for specific path attributes (setup time, hold time, clock-to-output time). Instead of one general-purpose storage element, the system creates specialized variants that can be selected based on the specific timing requirements of different circuit paths, thereby achieving path-specific optimization without overwhelming complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by making different parts of the storage element library have different functions optimized for different local conditions. Each storage element variant is optimized for specific local path attributes (e.g., one variant for setup time critical paths, another for hold time critical paths), allowing the circuit to achieve optimal performance in each specific location rather than using a uniform approach throughout.

Inventive Principle:
Principle #3Local quality

2Speed

If circuit designs use blanket optimizations for storage elements, then design simplicity is maintained, but circuit speed and efficiency are compromised

Engineering Contradiction:
Improvecircuit speedVSAvoidstorage element selection complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent introduces dynamics into the storage element selection process by making the optimization adaptable to different path conditions. The system dynamically selects appropriate storage element variants based on timing analysis results, allowing the circuit to achieve high speed performance while the complexity is managed through automated selection rather than manual design complexity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameters of storage elements to create specialized variants optimized for different timing attributes. By varying parameters such as setup time, hold time, and clock-to-output time characteristics, the system achieves improved circuit speed while the parameter variations are systematically managed through the optimization process rather than creating unmanageable design complexity.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If specialized storage elements are created for specific operational attributes, then timing precision is improved, but design and manufacturing complexity increases

Engineering Contradiction:
Improvetiming optimization precisionVSAvoidstorage element library development
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by pre-characterizing and pre-optimizing multiple storage element variants for different timing attributes before actual circuit design. The specialized storage elements are prepared in advance with known timing characteristics, allowing designers to simply select the appropriate variant based on path requirements rather than performing complex optimization during manufacturing, thereby achieving timing precision without increasing manufacturing complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses copying by creating multiple variants of storage elements that are based on a standard template but with modified parameters for specific attributes. Rather than designing entirely new complex structures for each specialization, the system copies the basic storage element design and adjusts specific parameters to create specialized variants, simplifying the overall development process while maintaining timing precision.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS8667449B2Flip-flop library development for high frequency designs built in an ASIC flow
Publication Date: 2014.03.04 ADVANCED MICRO DEVICES INC
  • US8667449B2 patent drawing
  • US8667449B2 patent drawing
  • US8667449B2 patent drawing

AI summary

A method, computer program storage device and system are provided for determination and selection of optimized circuit components. The method includes performing a timing analysis on at least a portion of an electronic circuit and determining a path in the at least a portion of an electronic circuit, where the path comprises at least one storage element and an operational attribute associated with the path. The method also includes determining an optimized storage element adapted to utilize the operational attribute. The system includes a processing device and at least one of a synthesis tool, a timing tool or a place and route tool communicatively connected to the processing device. The synthesis tool, the timing tool and the place and route tool are adapted to process or analyze an electrical circuit. The system also includes a gate library communicatively connected to the at least one of a synthesis tool, a timing tool and a place r route tool, as well as a substitution unit communicatively connected to at least one of the at least one of a synthesis tool, a timing tool or a place and route tool or the gate library. The substitution unit is adapted to substitute an optimized storage element for a storage element in the electrical circuit.