Edge-Triggered Flip-Flop Circuit for Low-Power High-Frequency Latching
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Solution Overview
Problem
Conventional master-slave flip-flops consume power due to internal nodes being repeatedly charged and discharged, even when input data is not changed, which is not suitable for low-power mobile devices with high operating frequencies.
Innovation Solution
A flip-flop design that includes internal nodes charged by inverted and regular input data, with cross-connected nodes to prevent unnecessary power consumption by avoiding repeated charging and discharging during unchanged input data, utilizing NMOS transistors and logic gates to latch data at rising clock edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional master-slave flip-flop is used, then the flip-flop has high reliability and small size, but the flip-flop consumes power due to internal nodes being repeatedly charged and discharged even when input data is not changed
Solution Approach 1:
The patent implements periodic action by using clock signal edges (rising and falling edges) to control when internal nodes are charged or discharged. The flip-flop is designed to update internal nodes only at specific clock transitions rather than continuously, thereby reducing unnecessary charging/discharging cycles. This periodic control mechanism allows the circuit to maintain functionality at high operating frequencies while minimizing power consumption during stable input conditions.
Solution Approach 2:
The patent applies local quality by differentiating the charging/discharging behavior of different internal nodes based on their specific functions and clock edge responses. Some nodes are charged on rising edges while others are charged on falling edges, and not all nodes are updated on every clock cycle. This localized control strategy ensures that only necessary nodes are actively updated, reducing overall power consumption while maintaining the reliability and speed requirements for mobile devices.
2Speed
If internal nodes are repeatedly charged and discharged in response to clock signal, then the flip-flop can maintain operation at high frequencies, but power consumption increases
Solution Approach 1:
The patent implements periodic action by using clock signal edges (rising and falling edges) to control when internal nodes are charged or discharged. The flip-flop is designed to update internal nodes only at specific clock transitions rather than continuously, thereby reducing unnecessary charging/discharging cycles. This periodic control mechanism allows the circuit to maintain functionality at high operating frequencies while minimizing power consumption during stable input conditions.
Solution Approach 2:
The patent applies dynamics by making the charging/discharging behavior of internal nodes adaptive to the input data conditions. When input data remains unchanged, the circuit dynamically prevents unnecessary charging/discharging operations. The NMOS transistors and logic gates are configured to respond dynamically to data transitions, enabling the flip-flop to adjust its activity level based on actual operational needs, thus reducing power consumption while maintaining high-frequency capability.
Data Source
AI summary
A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.