Master-Slave Flip-Flop Clocking for Lower Vmin Operation
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Solution Overview
Problem
Existing flip-flop circuits are limited by minimum operating voltage and energy dissipation, leading to incorrect data storage at voltages below the minimum operating voltage.
Innovation Solution
The proposed flip-flop design incorporates a multiplexing device and latching circuits with phase shift circuits and feedback circuits controlled by advanced clock signals to prevent signal conflicts and jitters, allowing operation at lower voltages by improving the minimum operating voltage (Vmin) by 25-50 mV.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional flip-flop circuits are used, then data storage function is provided, but the minimum operating voltage is high and energy dissipation is excessive
Solution Approach 1:
The flip-flop circuit is divided into a master latch and a slave latch, each with separate feedback circuits. This segmentation allows independent optimization of each latch's voltage requirements and feedback control, enabling the overall circuit to operate at lower voltages while maintaining data storage reliability through coordinated master-slave operation.
Solution Approach 2:
Feedback circuits are implemented in both the master latch and slave latch, with feedback signals controlled by clock phases. The feedback mechanisms maintain stable latch states and prevent signal conflicts, enabling reliable data storage at reduced operating voltages by actively correcting state deviations through controlled feedback paths.
2Loss of energy
If the operating voltage is reduced below the minimum operating voltage, then power consumption decreases, but data storage becomes incorrect
Solution Approach 1:
Clock signals are advanced relative to the data signal to pre-establish the proper latch state before the data arrives. This preliminary action ensures that the feedback circuits are already configured correctly to capture and hold the data bit, maintaining storage accuracy even at reduced operating voltages where timing margins are tighter.
Solution Approach 2:
The circuit utilizes phase shifting of clock signals as a control parameter to optimize the timing and voltage requirements. By adjusting the phase relationship between clock signals and data signals, the circuit achieves reliable latching at lower voltage levels, effectively changing the operational parameters to enable low-voltage operation without sacrificing data storage accuracy.
3Reliability
If feedback circuits are added to prevent signal conflicts, then circuit reliability improves, but device complexity increases
Solution Approach 1:
The feedback circuits are merged with the clock signal distribution network, where the same clock phases that control latch enablement also control feedback path activation. This integration eliminates the need for separate feedback control signals, reducing overall circuit complexity while maintaining signal stability through unified clock-driven feedback management.
Data Source
AI summary
A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master latch including a feedback circuit, and a slave latch including a feedback inverter. The feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, the feedback circuit includes a third transistor configured to receive the second clock signal, and the slave latch is configured to receive the third clock signal.