Flip-Flop Synchronizer Biasing for Metastability Control
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Solution Overview
Problem
Conventional synchronizers face challenges in minimizing the metastability resolving timing constant (Tau) without increasing the number of stages or altering system requirements, particularly in systems-on-chip (SoC) with asynchronous signals, leading to high Tau values and increased power consumption.
Innovation Solution
The implementation of NWell and PWell forward biasing techniques, as well as mixed voltage threshold technologies, to optimize flip-flop circuitry, reducing Tau values and improving Mean Time Between Failures (MTBF) by adjusting biasing voltages and using low voltage threshold (LVT) technology for timing-critical components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional synchronizer designs are used, then the system can handle asynchronous signals, but the metastability resolving timing constant (Tau) is high and power consumption is high
Solution Approach 1:
The patent applies parameter changes by adjusting the biasing voltages of the NWell and PWell regions in the flip-flop circuitry. By changing the voltage parameters (applying forward biasing voltages), the patent optimizes the metastability resolving characteristics and reduces power consumption without altering the fundamental synchronizer architecture or increasing the number of stages.
2Reliability
If the number of synchronizer stages is increased to reduce Tau, then metastability is better resolved, but device complexity and area increase
Solution Approach 1:
Instead of increasing the number of synchronizer stages, the patent resolves metastability more effectively by changing the electrical parameters of existing flip-flops through NWell and PWell forward biasing. This approach achieves better metastability resolution while maintaining the same number of stages, thereby reducing device complexity and area.
3Reliability
If forward biasing voltages are applied to NWell and PWell, then Tau values are reduced and MTBF is enhanced, but power consumption increases
Solution Approach 1:
The patent optimizes the forward biasing voltages applied to NWell and PWell regions to achieve the best balance between MTBF enhancement and power consumption. By carefully selecting and adjusting the voltage parameters, the patent reduces Tau values and improves reliability while minimizing the additional power consumption associated with forward biasing.
Data Source
AI summary
Synchronizer circuits having controllable metastability are provided, one of which includes: a first flip-flop circuit comprising a first master latch connected in series with a first slave latch; and a second flip-flop circuit comprising a second master latch connected in series with a second slave latch, wherein an output of the first flip-flop circuit is connected to an input of the second flip-flop circuit, at least a portion of the first flip-flop circuit is implemented in a first PWell isolated by an underlying a deep isolation NWell, at least a portion of the first flip-flop circuit is implemented in a first NWell that electrically contacts the deep isolation NWell, the first NWell is connected to a first bias voltage that is less than a positive power supply voltage, and the first PWell is connected to a second bias voltage that is greater than a negative power supply voltage.