Master-Slave Flip-Flop Latch Using Mixed Transistor Widths
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Solution Overview
Problem
The miniaturization of integrated circuits poses challenges in design and manufacturing, requiring stricter specifications and reliability, particularly in reducing time delays in flip-flop circuits while maintaining power efficiency and functionality.
Innovation Solution
The use of wide transistors in wide active-region structures for class-one devices and narrow transistors in narrow active-region structures for class-two devices in master-slave flip-flop circuits, along with specific configurations of inverters and transmission gates, reduces time delays and improves setup slack times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If miniaturization is applied to integrated circuits, then power consumption is reduced and functionality is increased, but time delays in flip-flop circuits increase and manufacturing precision requirements become stricter
Solution Approach 1:
The patent applies different transistor widths to different functional blocks within the flip-flop circuit. Class-one devices (first inverter, first transmission gate, second inverter) use wide transistors to minimize delay, while class-two devices (first clocked inverter, second clocked inverter) use narrow transistors to save area. This local differentiation resolves the contradiction by optimizing delay only where critical while maintaining overall miniaturization benefits.
2Area of moving object
If transistor sizes are reduced for miniaturization, then area is reduced, but time delays in signal propagation increase
Solution Approach 1:
The patent strategically places wide transistors only in critical delay paths (class-one devices) while using narrow transistors in non-critical areas (class-two devices). This localized approach minimizes area while preventing delay increase in signal propagation paths that matter most for circuit performance.
Solution Approach 2:
The flip-flop circuit is segmented into class-one and class-two devices based on their functional importance. Class-one devices form the critical data path with wide transistors for speed, while class-two devices handle clocking and control functions with narrow transistors for area efficiency. This segmentation allows the circuit to achieve miniaturization without compromising signal propagation delay in critical paths.
3Ease of manufacture
If uniform transistor sizes are used, then manufacturing is simpler, but time delays cannot be optimized for different functional blocks
Solution Approach 1:
The patent uses two discrete transistor width sizes (wide and narrow) rather than a continuous range, which maintains manufacturing simplicity while enabling delay optimization. The manufacturing process remains relatively simple with clear design rules distinguishing class-one and class-two devices, yet the circuit achieves differentiated performance in different functional blocks through this binary classification.
Data Source
AI summary
An integrated circuit includes a first inverter, a first transmission gate, and a second inverter constructed with wide type-one transistors and wide type-two transistors. The integrated circuit also includes a first clocked inverter and a second clocked inverter constructed with narrow type-one transistors and narrow type-two transistors. A master latch is formed with the first inverter and the first clocked inverter. A slave latch is formed with the second inverter and the second clocked inverter. The first transmission gate is coupled between the master latch and the slave latch. The wide type-one transistors are formed in a wide type-one active-region structure and the narrow type-one transistors are formed in a narrow type-one active-region structure. The wide type-two transistors are formed in a wide type-two active-region structure and the narrow type-two transistors are formed in in a narrow type-two active-region structure.