Flip-Flop Toggle Feedback to Suppress NBTI in Low-Power ICs
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Solution Overview
Problem
Semiconductor integrated circuits face performance degradation due to negative bias temperature instability (NBTI) in PMOS transistors, leading to increased circuit size, cost, and prolonged development periods, as existing methods either overcompensate with timing margins or fail to address data path degradation.
Innovation Solution
Incorporating selectors in flip-flop circuits to switch between normal and low power consumption modes, ensuring a clock signal is always active and not fixed, and using a toggle signal in data paths to prevent NBTI degradation by maintaining current flow in PMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timing analysis is performed in low power consumption mode to account for NBTI degradation, then reliability is improved, but device complexity and development time increase due to over margin generation
Solution Approach 1:
The patent applies preliminary action by forcing a toggle signal through the data path during low power consumption mode before normal operation begins. This pre-active operation prevents NBTI degradation from occurring in the first place, eliminating the need for subsequent timing analysis and over margin design. The selector circuit is configured in advance to route the toggle signal, and PMOS transistors are kept active before they would otherwise be subjected to fixed negative bias conditions.
2Use of energy by moving object
If fixed-value negative bias voltage is applied to PMOS gate electrode in low power consumption mode, then power consumption is reduced, but NBTI degradation occurs causing performance deterioration
Solution Approach 1:
The patent applies periodic action by generating a toggle signal that alternates between high and low levels with a certain period during low power consumption mode. This periodic switching keeps the PMOS transistor in the data path actively switching rather than being held in a fixed negative bias state. The toggle signal is generated by routing the inverted output of the flip-flop back through the data path, creating continuous periodic operation that prevents NBTI degradation while maintaining low average power consumption.
Solution Approach 2:
The patent applies inversion by using the inverted output of the flip-flop circuit (Q-bar) as the input to the data path during low power consumption mode. Instead of applying a fixed low level that would put PMOS in negative bias, the inverted output provides a toggling signal. This inverted signal approach ensures PMOS transistors remain active and switching, preventing NBTI while still achieving low power consumption through the efficient use of existing flip-flop output signals.
3Reliability
If NBTI degradation occurs in data path, then setup time margin decreases, but existing methods increase circuit size to compensate
Solution Approach 1:
The patent applies preliminary action by pre-activating PMOS transistors in the data path through toggle signal operation during low power consumption mode. This preliminary activation prevents NBTI degradation before it can affect setup time margins. By keeping PMOS transistors actively switching rather than in fixed negative bias, the transistors maintain their original threshold voltages and drive currents, ensuring adequate setup time margins without requiring additional timing margin compensation or larger circuit sizes.
4Reliability
If NBTI degradation occurs in clock path, then clock skew increases causing erroneous operation, but preventing it increases development period and cost
Solution Approach 1:
The patent applies universality by using the same selector circuit and toggle signal mechanism for both clock path and data path protection against NBTI. The operation-mode switching signal controls selectors in both paths simultaneously, providing unified NBTI prevention. This multi-functional approach protects both clock and data paths using a single control mechanism, avoiding the need for separate protection circuits and reducing overall development complexity and time.
Data Source
AI summary
A semiconductor integrated circuit device includes a target circuit of a low power consumption mode having at least one flip-flop circuit to which a clock signal is supplied in a normal operation mode and in a low power consumption mode, and a logic circuit to which each output of the at least one flip-flop circuit is input, wherein each of the flip-flop circuits includes a selector that selects a normal data signal in the normal operation mode, selects an inverted output of the flip-flop circuit in the low power consumption mode, based on an operation-mode switching signal that designates switching between the normal operation mode and the low power consumption mode, and inputs the selected signal to a data input terminal of the flip-flop circuit.