Edge-Triggered Flip-Flop Layout for Lower Internal Node Switching
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Solution Overview
Problem
Conventional master-slave flip-flops consume power due to internal nodes being repeatedly charged and discharged, even when input data is not changed, which is not suitable for low-power mobile devices with high operating frequencies.
Innovation Solution
A flip-flop design that includes internal nodes charged by inverted and regular input data, where these nodes are cross-connected to prevent unnecessary power consumption by not charging and discharging when data is unchanged, using a combination of NMOS transistors and logic gates to latch data at rising clock edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional master-slave flip-flop is used, then the size is relatively small and reliability is high, but power consumption increases due to internal nodes being repeatedly charged and discharged
Solution Approach 1:
The patent removes the clocked internal nodes that are repeatedly charged and discharged in conventional master-slave flip-flops. By extracting these power-consuming elements and replacing them with a different architecture using transmission gates and latching mechanisms, the design eliminates unnecessary power consumption while maintaining functionality at high operating frequencies.
Solution Approach 2:
The patent employs dynamic control of transmission gates using clock signals to enable data transfer only during required periods. The transmission gates are dynamically switched based on clock phases, allowing data to pass through only when needed, thereby preventing continuous charging and discharging of nodes while maintaining high-speed operation.
2Reliability
If internal nodes are repeatedly charged and discharged in response to clock signal, then data latching function is achieved, but power consumption increases
Solution Approach 1:
The patent uses periodic clock signals to control transmission gates in a master-slave configuration, where data is transferred during specific clock phases and held during others. This periodic action ensures reliable data latching while minimizing the duration that nodes remain charged, thereby reducing overall power consumption compared to continuous charging schemes.
Solution Approach 2:
The patent introduces transmission gates as intermediary elements between the clock signal and the internal nodes. These transmission gates act as controlled switches that mediate the charging of nodes only when data transfer is required, preventing direct and continuous charging of nodes by the clock signal, thus reducing power consumption while maintaining latching reliability.
3Speed
If the flip-flop operates at high frequency, then processing speed is improved, but power consumption increases due to repeated charging and discharging
Solution Approach 1:
The patent maintains continuous useful action by ensuring that data transfer occurs efficiently during active clock phases without requiring repeated full charging and discharging cycles. The latching mechanism holds data steadily during non-transfer phases, eliminating redundant charging operations while maintaining high processing speed through optimized data path design and transmission gate control.
Data Source
AI summary
A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.