Dynamic Flip-Flop P-Stack Feedback for Lower Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional flip flops face challenges with increased setup requirements due to multiple signals converging, leading to taller and wider P-stacks, which result in higher capacitance and bottlenecks in circuit design, particularly with negative setup slack and race conditions.
Innovation Solution
A dynamic flip flop with a data-independent P-stack feedback mechanism, incorporating a first P-type transistor gated by a dynamic inverted net signal and a second P-type transistor gated by an inverted clock signal, where the source of the second transistor is directly coupled to a node receiving a second dynamic inverted net signal, eliminating the need for additional PMOS devices and integrating delay stages to prevent race conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple signals are converged onto a single flip flop to handle complex circuit architectures, then the circuit functionality is improved, but the P-stack becomes taller and wider increasing total capacitance and creating setup bottlenecks
Solution Approach 1:
The feedback path is segmented into two independent P-stacks: a data-dependent P-stack for normal operation and a data-independent P-stack for feedback. This segmentation allows the feedback signal to bypass the data convergence path, preventing the P-stack from becoming taller and wider while maintaining circuit functionality.
Solution Approach 2:
A data-independent feedback path acts as an intermediary mechanism that carries the feedback signal separately from the data convergence path. This intermediary path eliminates the need for multiple data signals to converge through a single tall P-stack, reducing capacitance while preserving circuit adaptability.
2Reliability
If the P-stack is made taller to accommodate more feedback signals, then feedback accuracy is improved, but the total capacitance increases leading to slower clock-to-output speed
Solution Approach 1:
The feedback mechanism is segmented into data-dependent and data-independent paths. The data-independent path provides accurate feedback without requiring a tall P-stack, as it uses a separate, optimized feedback path that does not carry multiple converging data signals.
Solution Approach 2:
The feedback signal is routed through a separate dimensional path (data-independent feedback path) rather than being forced through the data convergence path. This dimensional separation allows feedback accuracy to be maintained without increasing P-stack height, thereby preserving clock-to-output speed.
3Adaptability or versatility
If additional PMOS devices are added to the P-stack to handle more inputs, then the circuit can accommodate more signals, but the leakage power increases
Solution Approach 1:
The circuit is segmented into data-dependent and data-independent paths. The data-independent feedback path requires minimal PMOS devices, significantly reducing leakage power compared to a single P-stack handling all signals. The segmentation allows signal handling capability to be maintained while minimizing the number of active PMOS devices in any given path.
Solution Approach 2:
The feedback function is extracted from the data convergence path and placed in a separate data-independent path. This extraction removes the need for additional PMOS devices in the main data path, reducing total leakage power while maintaining the ability to handle multiple signals through the separated paths.
4Loss of time
If the N:1 MUX is integrated into the flip flop to reduce setup requirements, then setup benefit is improved, but a larger number of signals converge into the flip flop making the P-stack taller and the N-stack wider
Solution Approach 1:
The integrated MUX and flip-flop circuit is segmented into data-dependent and data-independent paths. The feedback path is separated into a dedicated data-independent P-stack that does not converge with data signals, allowing the N:1 MUX to be integrated without increasing the height of the feedback P-stack or the width of the data N-stack.
Solution Approach 2:
A data-independent feedback path serves as an intermediary that carries feedback signals separately from the data convergence path through the integrated MUX-flip-flop structure. This intermediary path enables setup time optimization through integration while preventing the feedback P-stack from becoming taller due to signal convergence.
Data Source
AI summary
Inventive aspects include a dynamic flip flop, comprising a data independent P-stack feedback circuit. The data independent P-stack feedback circuit may include a first P-type transistor gated by a first dynamic inverted net signal, and a second P-type transistor gated by an inverted clock signal. A drain of the second P-type transistor may be coupled to a source of the first P-type transistor. A source of the second P-type transistor may be coupled to a node that is configured to receive a second dynamic inverted net signal. The source of the second P-type transistor may be directly coupled to the node that is configured to receive the second dynamic inverted net signal instead of a constant power source. The data independent P-stack feedback circuit may include one or more delay stages to eliminate race conditions.