State-Retention Flip-Flop for Power-Down Logic Hold

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Solution Overview

Problem

Existing flip-flops face challenges in retaining logic states during power down mode, leading to potential data loss and undesirable clock state restrictions, which can limit their application in reducing leakage current and extending battery life in handheld devices.

Innovation Solution

A state retention flip-flop design featuring a master latch and a slave latch connected through an inverter, where the slave latch retains the logic state during power down mode and feeds it back to the master latch upon power restoration, allowing seamless entry and exit from power down mode without clock state restrictions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If power is cut off to reduce leakage current, then power consumption is reduced, but logic state is lost

Engineering Contradiction:

Improvepower consumptionVSAvoidlogic state

Core Design Contradiction:

Use of energy by moving objectVSLoss of information

Solution Approach 1:

The flip-flop is divided into two separate latches: a master latch that can be powered down and a slave latch that retains the logic state during power down mode. This segmentation allows different parts of the circuit to have different power states simultaneously, enabling leakage reduction while preserving data.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The slave latch acts as an intermediary that temporarily holds the logic state when the master latch is powered down. It mediates between the powered-down master latch and the output circuit, ensuring state retention without requiring continuous power to the entire flip-flop.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If a separate latch is added to retain logic state, then logic state retention is achieved, but device complexity increases

Engineering Contradiction:

Improvelogic state retentionVSAvoidcircuit structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The master and slave latches are merged into a single integrated flip-flop structure with shared control logic and interconnections. The latches work together as a unified system rather than separate components, reducing overall complexity while maintaining state retention functionality.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The slave latch serves multiple functions: it retains logic state during power down, provides feedback to the master latch upon power restoration, and maintains circuit operation during mode transitions. This multi-functionality reduces the need for additional dedicated components.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Use of energy by moving object

If threshold voltage is increased to reduce leakage current, then leakage current is reduced, but operating speed decreases

Engineering Contradiction:

Improveleakage currentVSAvoidoperating speed

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The flip-flop operates in periodic cycles, alternating between normal mode and power down mode. During normal mode, the circuit operates at full speed with standard threshold voltages. During power down mode, the master latch is powered off to eliminate leakage, while the slave latch maintains the state. This periodic switching allows the circuit to achieve both high speed operation and low leakage current.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS7583121B2Flip-flop having logic state retention during a power down mode and method therefor

Publication Date: 2009.09.01 NXP USA INC

AI summary

A flip-flop includes a master latch, a first inverter, a slave latch, and a first clocked inverter. The master latch has an input for receiving an input signal and an output. The first inverter has an input coupled to the output of the master latch and an output for providing an output of the flip-flop. The slave latch is directly connected to the input of the first inverter. The first clocked inverter has an input directly connected to the slave latch and an output coupled to the master latch.