Scannable Flip-Flop Power Reduction via Dynamic Selection Circuit
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Solution Overview
Problem
Scannable flip-flops in integrated circuits face power consumption issues during scan mode, often requiring additional circuitry like delay circuits to prevent data corruption, which increases power and area usage.
Innovation Solution
A system utilizing a selection circuit powered by multiple voltage signals, including a high voltage, low voltage, and a voltage that switches between them, to selectively route data signals based on a scan enable signal, reducing the need for additional circuitry and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional delay circuits are added to prevent data corruption in scan mode, then data integrity is improved, but power consumption and area usage increase
Solution Approach 1:
The patent extracts and removes the unnecessary delay circuits from the scan chain configuration. By taking out these additional components that were originally added to prevent data corruption, the invention eliminates their power consumption and area overhead while maintaining data integrity through the selective coupling mechanism controlled by the scan enable signal.
Solution Approach 2:
The invention dynamically reconfigures the flip-flop coupling based on the scan enable signal. During scan mode, flip-flops are dynamically coupled to form the scan chain for testing. During normal operation, they are dynamically decoupled from the scan chain and connected to their functional logic. This dynamic reconfiguration eliminates the need for static delay circuits, reducing both power consumption and area while maintaining data integrity in both modes.
2Reliability
If additional delay circuits are added to prevent data corruption in scan mode, then data integrity is improved, but area usage increases
Solution Approach 1:
The patent extracts and removes the unnecessary delay circuits from the scan chain configuration. By taking out these additional components that were originally added to prevent data corruption, the invention eliminates their area overhead while maintaining data integrity through the selective coupling mechanism controlled by the scan enable signal.
Solution Approach 2:
The scan enable signal serves multiple functions: it controls the selection between scan mode and normal operation mode, and it dynamically manages the coupling of flip-flops to the scan chain. This multi-functionality eliminates the need for separate delay circuit components, reducing area usage while maintaining data integrity through proper mode switching.
3Stability of the object's composition
If scan chains operate on the core clock, then synchronization is improved, but power consumption increases
Solution Approach 1:
The invention uses periodic action by enabling the scan chain operation only during specific test periods when the scan enable signal is active. During normal operation periods, the scan chain is disabled and flip-flops operate in their functional mode. This periodic activation reduces power consumption compared to continuous operation on the core clock, while maintaining synchronization during the actual scan operations.
Data Source
AI summary
According to one general aspect, an apparatus may include a first power signal having a high voltage. The apparatus may include a second power signal having a low voltage. The apparatus may include a third power signal having a voltage configured to switch between the high voltage and the low voltage. The apparatus may include a latching circuit powered by the first power signal and the second power signal. The apparatus may include a selection circuit configured to select between, at least, a first data signal and a second data signal, and powered by the first power signal, the second power signal, and the third power signal.