Flip-Flop Clock Pulse Inflation for Higher Frequency Operation
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Solution Overview
Problem
High-speed flip-flops face limitations in maximum clock frequency due to increased low pulse width (LPW) requirements, which are exacerbated by delayed clock signals and a greater number of transistors in the falling signal path, leading to reduced low pulse width relative to high pulse width, limiting system performance.
Innovation Solution
A flip-flop circuit configuration that generates inflated low pulse width (LPW) and high pulse width (HPW) clock signals by creating a clock buffer signal with delayed pulses, allowing for increased LPW and HPW durations, thereby reducing the LPW requirement on the primary clock pin and enhancing the maximum operating frequency without affecting set-up/hold times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If delayed clock signals are used to improve set-up time in high-speed flip-flops, then set-up time is improved, but low pulse width is reduced
Solution Approach 1:
The patent introduces an intermediary circuit (pulse width adjustment circuit) that receives the delayed clock signal and actively extends its low pulse width. This intermediary component decouples the relationship between delay improvement and pulse width reduction, allowing the clock signal to benefit from delay optimization while the circuit compensates for the pulse width reduction.
Solution Approach 2:
The patent changes the temporal parameters of the clock signal by dynamically adjusting the low pulse width through control logic. The circuit monitors the delayed clock signal characteristics and modifies the pulse width parameter to compensate for the reduction caused by signal delay, thereby maintaining adequate pulse width despite the delay optimization.
2Speed
If more transistors are used in the falling signal path to improve switching performance, then switching performance is improved, but low pulse width is further reduced
Solution Approach 1:
The patent converts the harmful effect of reduced low pulse width (caused by additional transistors in the falling path) into a benefit by using the same transistor count increase to implement a compensation mechanism. The additional transistors are utilized to create control logic that actively extends the low pulse width, transforming the original problem into a solution.
Solution Approach 2:
The patent introduces a mediator circuit that sits between the falling signal path and the output, monitoring the pulse width reduction caused by the additional transistors and actively compensating for it. This intermediary layer decouples the switching performance improvement from the pulse width degradation.
3Duration of action of moving object
If higher low pulse width requirement is accepted to maintain adequate pulse width, then low pulse width is maintained, but maximum clock frequency is limited
Solution Approach 1:
The patent makes the low pulse width dynamic rather than static, allowing it to adapt to the actual delay characteristics of the clock signal path. The control logic dynamically adjusts the pulse width extension based on real-time signal characteristics, enabling the system to maintain adequate pulse width at higher clock frequencies without being constrained by fixed timing requirements.
Solution Approach 2:
The patent changes the low pulse width parameter dynamically based on the operating conditions and clock frequency. By using control logic that monitors signal characteristics and adjusts the pulse width accordingly, the system can maintain adequate pulse width at higher frequencies rather than being limited by a fixed conservative timing requirement.
Data Source
AI summary
Example flip-flops comprise a circuit that receives a primary clock signal, generates a clock buffer signal having a series of pulses, each delayed by a set amount of time relative to a corresponding pulse of the primary clock signal, generates an intermediate clock signal based on the primary clock signal and the clock buffer signal, generates inflated low pulse width clock signals, each having a low pulse width that is greater than a low pulse width of the primary clock signal. Latch stages within example flip-flops include one or more components that are controlled by the inflated low pulse width clock signals. Example flip-flops include high-speed flip-flops and standard flip-flops. Larger circuits, such as a clock divider circuits, may incorporate multiple example high-speed flip-flops to improve performance.