Flip-Flop Pulse Generator With Trimmable Clock Pulse Width
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Solution Overview
Problem
Current pulse generator designs are limited in their ability to trim the output clock signal pulse width up to a full input clock signal period, preventing flexible adjustment of the calibration interval and precise control of the clock signal.
Innovation Solution
A flop-based clock pulse generator circuit that includes a flip-flop receiving an input clock signal and one or more delay elements, allowing the circuit to adjust the pulse width of the output clock signal independent of the clock period of the input clock signal, and to trim the calibration interval based on the trimmable output clock pulse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the output clock signal pulse width is limited to half the input clock signal period, then the circuit operation is simplified, but the flexibility and precision of clock signal management is reduced
Solution Approach 1:
The patent implements dynamic adjustability of the output clock signal pulse width by allowing it to extend beyond half the input clock period up to the full period. This is achieved through controllable delay elements that can dynamically adjust the pulse width based on system requirements, transforming a static limitation into a dynamic adjustable parameter.
Solution Approach 2:
The patent changes the key parameter of pulse width from a fixed value (half period) to a variable parameter that can be adjusted between half period and full period. This parameter change enables flexible control of the calibration interval and improves clock signal management precision without fundamentally changing the circuit architecture.
2Measurement precision
If the calibration interval cannot be trimmed, then the circuit design is simpler, but the precision of clock signal control is reduced
Solution Approach 1:
The calibration interval is transformed from a fixed value to a dynamically trimmable parameter. The circuit enables continuous adjustment of the calibration interval by controlling the output pulse width, allowing precise optimization of clock signal timing characteristics for different application requirements.
Solution Approach 2:
The circuit enables self-calibration capability by allowing the calibration interval to be trimmed based on actual system performance. This self-service mechanism allows the system to automatically optimize its own timing parameters without external intervention, improving precision while maintaining reasonable circuit complexity.
Data Source
AI summary
According to one implementation, a pulse generator circuit includes a flip-flop receiving an input clock signal, and one or more delay elements where the circuit is configured to adjust a pulse width of an output clock signal independent of a clock period of the input clock signal. According to another implementation, a pulse generator circuit includes a flip-flop receiving an input clock signal, and one or more delay elements where the circuit is configured to adjust a pulse width of an output clock signal. The flip-flop is configured to transmit a flip-flop output signal to the one or more delay elements where the flip-flop output signal includes a state of the flip-flop. The one or more delay elements are configured to delay the flip-flop output signal by a delay period and transmit the delayed flip-flop output to a reset input.