Master-Slave Flip-Flop Circuit for Lower RC Delay

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Solution Overview

Problem

The miniaturization of integrated circuits (ICs) has led to stricter design and manufacturing specifications, as well as reliability challenges, particularly in achieving optimal switching speeds and reducing RC delay in master-slave flip-flops.

Innovation Solution

The implementation of master-slave flip-flops that incorporate both strong and weak transistors, with strong transistors used in forwarding-switches and weak transistors used in clocked inverters, to reduce RC delay while maintaining improved switching speeds.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If miniaturization is pursued to reduce device size and power consumption, then device size and power consumption are reduced, but RC delay increases and switching speeds deteriorate

Engineering Contradiction:

Improvedevice sizeVSAvoidswitching speed

Core Design Contradiction:

Volume of moving objectVSSpeed

Solution Approach 1:

The patent applies local quality by using strong transistors specifically in the forwarding-switch portion of the flip-flop circuit while using weak transistors in other portions. This localized differentiation allows the forwarding-switch to maintain strong driving capability and low RC delay despite overall miniaturization, thereby preserving switching speed in the critical signal path while still achieving reduced device size and power consumption.

Inventive Principle:

Principle #3Local quality

2Volume of moving object

If miniaturization is pursued to reduce device size, then device size is reduced, but RC delay increases

Engineering Contradiction:

Improvedevice sizeVSAvoidRC delay

Core Design Contradiction:

Volume of moving objectVSLoss of time

Solution Approach 1:

The patent implements local quality by differentiating transistor strength in specific circuit regions. Strong transistors are deployed in the forwarding-switch to minimize RC delay in the critical forward signal path, while weak transistors are used elsewhere to reduce overall device size. This localized optimization ensures that RC delay is minimized where it most impacts performance.

Inventive Principle:

Principle #3Local quality

3Speed

If strong transistors are used throughout the flip-flop, then switching speed is improved, but power consumption and device size increase

Engineering Contradiction:

Improveswitching speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by stationary object

Solution Approach 1:

The patent applies local quality by using strong transistors only in the forwarding-switch portion where high switching speed is critical, while using weak transistors in other portions of the flip-flop where full strength is not required. This selective approach maintains improved switching speed in the critical path while reducing overall power consumption and device size compared to using strong transistors throughout the entire circuit.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250183878A1Flip-flops having strong transistors and weak transistors

Publication Date: 2025.06.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An integrated circuit includes a first clocked forwarding-switch and a second clocked forwarding-switch each implemented with strong transistors. The integrated circuit also includes a first clocked inverter and a second clocked inverter each implemented with weak transistors. The integrated circuit further includes a first inverter cross coupled with the first clocked inverter and a second inverter cross coupled with the second clocked inverter. An output of the first clocked forwarding-switch is conductively connected with an output of the first clocked inverter, and an output of the second clocked forwarding-switch is conductively connected with an output of the second clocked inverter.