High-Speed Flip-Flop Circuit With Reduced Hold Time
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Solution Overview
Problem
Current semiconductor integrated circuits face challenges in achieving high-speed and high-integration performance due to the complexity of testing, which is exacerbated by the need for design for testability (DFT) technologies, particularly in the design and operation of flipflop circuits used in scan cell methods.
Innovation Solution
The proposed solution involves a high-speed flipflop circuit design that includes a clock circuit, signal generation circuits, and an output circuit, where the second signal generation circuit discharges a second signal line using a fourth signal derived from the first signal, enabling efficient data transfer and testability while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional flipflop structure is used to maintain testability through scan cell methods, then the circuit can be tested effectively, but the data transfer speed and hold time performance deteriorate
Solution Approach 1:
The flipflop circuit is divided into multiple independent signal generation circuits (first signal generation circuit, second signal generation circuit, third signal generation circuit), each handling specific signal paths. This segmentation allows parallel signal processing and reduces bottlenecks in the data transfer path, thereby improving speed while maintaining testability through dedicated scan input paths.
Solution Approach 2:
The patent introduces intermediate signals (first signal, second signal, third signal) that act as mediators between the clock circuit and the output circuit. These intermediate signals enable staged signal processing and provide additional control points for timing management, which improves data transfer speed while allowing separate test data paths to operate independently.
2Loss of time
If the hold time is reduced to improve data transfer speed, then the data-to-output operation becomes faster, but the reliability of data latching deteriorates
Solution Approach 1:
The first signal generation circuit generates control signals in advance based on the clock signal and input data, preparing the circuit state before the actual data latching occurs. This preliminary action allows the main data path to operate with reduced hold time while the pre-prepared control signals ensure reliable latching by establishing proper timing conditions beforehand.
Solution Approach 2:
The circuit employs feedback mechanisms where the output signals are fed back through the third signal generation circuit to control subsequent operations. This feedback ensures that data latching is confirmed and stabilized before proceeding to the next clock cycle, maintaining reliability even with reduced hold times by continuously monitoring and adjusting the latching state.
3Adaptability or versatility
If DFT technology is implemented with scan cell methods, then testability is improved, but the overall circuit complexity and testing resources increase
Solution Approach 1:
The signal generation circuits are designed to serve dual purposes: they handle normal data transfer operations during circuit operation and simultaneously support test operations when scan input signals are applied. The same circuit structures process both functional data and test data, eliminating the need for completely separate test circuits and reducing overall complexity while maintaining full testability.
Data Source
AI summary
High-speed flipflop circuits are disclosed. The flipflop circuit may latch a data input signal or a scan input signal using a first signal, a second signal, a third signal, and a fourth signal generated inside the flipflop circuit, and may output an output signal and an inverted output signal. The flipflop circuit includes a first signal generation circuit configured to generate the first signal; a second signal generation circuit configured to generate the second signal; a third signal generation circuit configured to receive the second signal and generate the third signal; and an output circuit configured to receive the clock signal and the second signal, and output an output signal and an inverted output signal.