Multi-bit Flip Flop Remapping for Timing Optimization
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Solution Overview
Problem
The process of banking, de-banking, and re-banking multi-bit flip-flops in electronics is computationally expensive and causes significant perturbation in chip layout, leading to increased wire delay and performance degradation due to displacement of components and adverse clock skew.
Innovation Solution
A remapping operation that identifies logically equivalent flops and reconfigures their physical locations without explicit de-banking and re-banking, using a bipartite graph formulation to optimize the mapping and rewiring of inputs and outputs to minimize wire length and timing differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If banking, de-banking, and re-banking operations are performed on multi-bit flip-flops, then timing performance may be improved, but computational cost increases and layout perturbation occurs
Solution Approach 1:
The patent segments the de-banking and re-banking operations into separate independent steps. The de-banking operation separates critical bits from non-critical bits in MBFFs, and the re-banking operation independently re-clusters the exploded fragments into new MBFF configurations. This segmentation allows each operation to be optimized separately, reducing overall computational complexity while maintaining timing performance benefits.
2Reliability
If de-banking and re-banking operations are performed, then timing criticality may be addressed, but wire delay increases due to component displacement
Solution Approach 1:
The patent performs preliminary actions by identifying and separating timing-critical bits during the de-banking phase before the re-banking phase begins. This preliminary identification allows the subsequent re-banking operation to strategically place critical bits in optimized positions while minimizing displacement of non-critical components, thereby reducing wire length increases and associated delays.
3Reliability
If multi-bit flip-flops are exploded and re-clustered, then timing optimization may be achieved, but clock skew increases due to layout perturbation
Solution Approach 1:
The patent applies local quality by treating timing-critical bits differently from non-critical bits throughout the de-banking and re-banking process. Critical bits receive specialized handling with prioritized placement strategies that maintain their proximity to clock sources and minimize displacement, while non-critical bits are re-clustered more freely. This localized optimization reduces clock skew for the most timing-sensitive elements while still achieving overall timing optimization.
4Productivity
If banking operations are performed, then routing efficiency may be improved, but manufacturing complexity increases
Solution Approach 1:
The patent introduces dynamics by making the banking configuration adaptive rather than fixed. The de-banking operation dynamically identifies which MBFFs should be exploded based on timing analysis, and the re-banking operation dynamically re-clusters bits into new MBFF configurations optimized for the specific design requirements. This dynamic approach allows the tool to achieve routing efficiency benefits of banking while avoiding the manufacturing complexity of fixed, universal banking structures.
Data Source
AI summary
Refining multi-bit flip flops mapping without explicit de-banking and re-banking is provided by identifying a set of equivalent flops in a layout, that include a first flop having a first logic routing and a first location in the layout and a second flop having a second logic routing and a second location in the layout; and remapping the first logic of the first flop from the first location to the second location and the second logic of the second flop from the second location to the first location.