Parallel Flip-Flop Reset Logic for Reliable Initialization Signals
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Solution Overview
Problem
Semiconductor devices face issues with power-on reset circuits failing to generate normal initialization signals under temperature or power supply conditions outside the guaranteed range, leading to unauthorized data access and potential program control errors.
Innovation Solution
A semiconductor device with multiple state holding circuits connected in parallel, and a logic circuit that generates a signal corresponding to the initialized state, increasing the probability of generating the correct initialization signal even under inappropriate conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single power-on reset circuit is used to generate initialization signals, then the device structure is simple, but the reliability of generating correct initialization signals under extreme temperature or power supply conditions deteriorates
Solution Approach 1:
The patent divides the reset circuit into multiple independent reset circuits (first reset circuit and second reset circuit), each capable of generating initialization signals independently. This segmentation increases reliability by ensuring that if one circuit fails under extreme conditions, the other can still generate the correct initialization signal, while maintaining manageable complexity through modular design
Solution Approach 2:
The patent introduces a detection circuit that monitors power supply voltage parameters and activates different reset circuits based on detected conditions. By changing the operational parameter (which reset circuit is activated) based on detected power supply state, the system maintains high reliability across varying operating conditions without requiring all circuits to function simultaneously
2Reliability
If multiple reset circuits are added to improve reliability, then the probability of generating correct initialization signal increases, but the device complexity increases
Solution Approach 1:
The patent extracts the essential function of generating initialization signals from the complex power-on reset circuit and implements it in simpler, dedicated reset circuits. By taking out the core functionality and separating it from the complex detection and control logic, the system achieves high reliability through multiple simple circuits rather than one complex circuit
Solution Approach 2:
The patent creates copies of the reset circuit functionality in multiple independent circuits. Each reset circuit is a functional copy that can independently generate the initialization signal, providing redundancy and increasing the probability of correct operation without requiring each copy to be more complex than the original
3Reliability
If the enable signal is not initialized properly, then data can be read from memory without restriction, but this creates security vulnerabilities and allows unauthorized access
Solution Approach 1:
The patent implements preliminary initialization of the enable signal before any data access operation can occur. By ensuring the enable signal is correctly initialized to its default state (preventing data read) before the CPU or other circuits attempt to access memory, the system proactively prevents unauthorized access rather than reacting after a security breach has occurred
Solution Approach 2:
The patent applies preliminary anti-action by using reset circuits that actively prevent unauthorized data access attempts before they can succeed. The reset circuits generate initialization signals that set the enable signal to block data reading, creating a preemptive barrier against security attacks rather than allowing access and then attempting to prevent it
Data Source
AI summary
To provide a semiconductor device which can perform initialization to a first state of two states of the first state and a second state, and which can generate a signal having a potential corresponding to the initialized first state. The present invention is the semiconductor device which can perform initialization to “0” (a first state) of two states of “0” and “1” (a second state), and which can generate a signal having a potential corresponding to initialized “0”. The semiconductor device 10 includes a plurality of flip-flop circuits 2 that are connected in parallel and which can hold the two states of “0” and “1”; and an AND circuit 3 which generates and outputs a signal having a potential corresponding to “0” when a state held in at least one flip-flop circuit 2 among the flip-flop circuits 2 is “0”. The AND circuit is connected to the flip-flop circuits 2.