Flip-Flop Scan Clock Generation for Timing Closure
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Solution Overview
Problem
Conventional flip-flop designs face challenges in achieving high-frequency operation due to limitations in timing closure, power consumption, and hold violations, particularly in scan mode, which require additional delay buffers that increase chip area and power usage.
Innovation Solution
A flip-flop architecture with a master-slave configuration and non-overlapping scan and functional mode clocks, allowing independent operation of scan and functional mode logic, eliminating the need for scan mode path delay buffers and reducing power consumption and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional flip-flop designs are used, then basic functionality is maintained, but timing closure is difficult to achieve at high frequencies
Solution Approach 1:
The flip-flop is divided into master and slave latches that operate independently with separate clocking. The master latch is clocked by a scan clock during scan mode, while the slave latch is clocked by the functional clock, allowing independent timing control for each mode and eliminating hold violations that plague conventional single-clock designs
Solution Approach 2:
The patent implements dynamic clock selection where the clock signal applied to the master latch changes based on operational mode. During scan mode, a scan clock is applied to the master latch, while during functional mode, the functional clock is applied, enabling the system to adapt its timing characteristics to the current operational requirements
2Reliability
If scan mode path delay buffers are added, then hold violations are prevented, but chip area and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the need for scan mode path delay buffers by implementing a different approach to hold violation prevention. Instead of adding buffers to delay scan signals, the invention uses separate clocking of master and slave latches to inherently prevent hold violations, thereby removing the need for additional delay buffer components
Solution Approach 2:
The patent converts the potential harm of hold violations into a beneficial design feature by using non-overlapping clocks. The scan clock and functional clock are designed to not overlap in time, which naturally prevents hold violations without requiring additional buffering, turning a problematic timing constraint into a design advantage
3Adaptability or versatility
If multiplexer is included in flip-flop, then scan and functional mode selection is enabled, but data path delay and setup time increase
Solution Approach 1:
The patent removes the multiplexer component entirely and replaces it with mode-select logic that controls clock gating. Instead of using a multiplexer to select between scan and functional data paths, the invention uses clock gating to separate the timing domains, eliminating the multiplexer's delay contribution while maintaining mode selection capability
Solution Approach 2:
The patent introduces clock gating logic as an intermediary mechanism between the clock signals and the latch inputs. This gating mechanism acts as a mediator that controls when each latch is active, replacing the multiplexer's data path selection function with a timing-based approach that avoids additional data path delays
4Reliability
If clock skew and jitter are present, then real-world timing variations occur, but minimum operating clock period increases
Solution Approach 1:
The patent segments the clocking into separate scan clock and functional clock domains with independent timing control. This segmentation allows each clock to be optimized for its specific purpose, with the scan clock designed to minimize scan mode hold violations and the functional clock optimized for functional operation, thereby reducing the impact of skew and jitter on the overall minimum operating clock period
Data Source
AI summary
A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of delay buffers in the scan mode data paths. Resulting application circuits have reduced circuit area, power consumption and noise generation. A clock generator for scan mode clocking is provided to obtain the separate, non-overlapping scan mode clocks. Scan mode clocks may be generated with a toggle flip flop, a pulse generator or a clock gating circuit.