Master-Slave Flip-Flop with Split Scan and Data Paths
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Solution Overview
Problem
Existing flip-flop circuits in high-performance microprocessors face challenges in reducing setup and hold times, clock-to-output times, and power consumption, while maintaining stable data signal input speeds and scan input signal paths.
Innovation Solution
The design incorporates a master latch, slave latch, and clock generator with independent scan and data paths, utilizing tri-state inverters and AOI circuits to optimize clock signals and reduce operation delays, allowing for faster data latch operations and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the scan path and data path are combined in a single input path, then the circuit complexity is reduced, but the data input speed and scan input signal stability cannot be optimized simultaneously
Solution Approach 1:
The input path is segmented into two independent paths: a scan path for scan input signals and a data path for data signals. Each path has its own optimization, allowing the scan path to maintain stable signal levels while the data path is optimized for high-speed data input, thereby resolving the contradiction between circuit complexity and data input speed.
2Productivity
If the setup time and hold time are reduced to increase clocking speed, then the logic clocking speed is improved, but the reliability of data latching may deteriorate
Solution Approach 1:
The circuit performs preliminary actions by pre-charging nodes and pre-positioning signals before the critical clock edge. The scan path signal is stabilized in advance, and the data path is prepared with proper timing margins, ensuring that even with reduced setup and hold times, the data latching remains reliable while achieving high clocking speeds.
3Speed
If the clock-to-output time is reduced to meet high-performance requirements, then the operation speed is improved, but the power consumption may increase due to faster switching
Solution Approach 1:
The circuit uses periodic clocked action with controlled switching phases. By organizing the latching operation around the clock cycle and using tri-state inverters that switch only at appropriate clock phases, the circuit achieves fast clock-to-output times while minimizing unnecessary switching activity, thereby reducing dynamic power consumption in high-performance operation.
4Speed
If tri-state inverters are used in the feedback path to enable high-speed operation, then the switching speed is improved, but the circuit complexity and power consumption increase
Solution Approach 1:
Tri-state inverters are applied locally and selectively in the feedback path rather than throughout the entire circuit. This localized application enables high-speed switching where it is most critical for maintaining signal integrity and timing, while avoiding unnecessary complexity and power consumption in other parts of the circuit where simpler structures suffice.
Data Source
AI summary
A flip-flop circuit includes a clock generator configured to generate first and second clock signals having different phases relative to each other, and a master-slave latch circuit including master and slave latches. The master latch includes a scan path configured to output a scan path signal in response to a scan enable signal and a scan input signal, and a data path configured to output a first latch signal in response to a data signal and the scan path signal. A feedback path is provided, which includes a tri-state inverter responsive to the first and second clock signals. The tri-state inverter has an input terminal connected to an output terminal of the data path and an output terminal connected to a node of the scan path.