Multi-Bit Flip-Flop Scan Path Delay for Hold Time Violations
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Solution Overview
Problem
Synchronous circuits in semiconductor devices face timing violations due to clock skew, which existing static timing analysis methods struggle to address effectively, particularly in hold time violations, requiring additional circuitry like buffers and OR gates to remedy.
Innovation Solution
The implementation of scan input circuitry within the flip-flop that delays the scan input signal, allowing for improved hold time by generating a delayed scan input signal, which is selectively provided to the master latch based on a scan enable signal, thereby enhancing the timing alignment and reducing hold time violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional circuitry like buffers and OR gates is added to remedy hold time violations, then hold time is improved, but device complexity increases
Solution Approach 1:
The patent combines the hold time correction function with the existing scan input circuitry by integrating a delay element directly into the scan path. This merges multiple functions (scan input handling and hold time adjustment) into a single integrated structure, avoiding the need for separate buffers and OR gates while still achieving the required hold time improvement
Solution Approach 2:
The scan input circuitry is designed to perform multiple functions: it handles scan input signals and simultaneously provides hold time correction through its integrated delay element. This multi-functional design eliminates the need for dedicated correction circuitry, reducing overall device complexity while maintaining reliability
2Reliability
If scan input signal delay is increased to address hold time violations, then timing alignment is improved, but signal propagation time increases
Solution Approach 1:
The delay is applied locally and selectively only to the scan input signal path where hold time violations occur, rather than introducing global delays to all signals. This localized approach improves timing alignment at the specific problem point without unnecessarily increasing overall signal propagation time across the entire circuit
Solution Approach 2:
The delay element is positioned upstream in the scan input path to preemptively adjust the signal timing before it reaches the flip-flop input. This preliminary timing adjustment prevents hold time violations from occurring in the first place, rather than requiring corrective action after the fact, thus optimizing overall signal propagation efficiency
Data Source
AI summary
Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.