Radiation-Hardened Flip-Flop With Interleaved SET Filtering
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Solution Overview
Problem
Existing radiation-hardened flip-flop circuits face challenges in mitigating single event transients (SETs) without significantly increasing power consumption, especially in bulk fin field-effect transistor technologies where spatial redundancy techniques are less effective.
Innovation Solution
A radiation-hardened flip-flop circuit design incorporating an interleaved filter and a feedback inverter, where the feedback inverter compares signals from a C-gate element and a blocking inverter to block transients from propagating, ensuring that only matching signals pass through, thereby preventing SETs from being captured as single event upsets (SEUs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spatial redundancy techniques (e.g., TMR) are used to mitigate SEUs, then SEU tolerance is improved, but power consumption increases significantly
Solution Approach 1:
The circuit is segmented into multiple functional blocks (interleaved filter with C-gate element, blocking inverter, feedback inverter) that work together to provide radiation hardening. Each segment performs a specific function in detecting and blocking SETs, allowing the system to achieve SEU tolerance without requiring full spatial redundancy of the entire flip-flop circuit.
Solution Approach 2:
The interleaved filter acts as an intermediary component between the data path and the flip-flop storage element. It includes a C-gate element and blocking inverter that detect and block SETs before they can propagate to and be captured by the flip-flop, thereby protecting the storage element without requiring redundant storage elements.
2Reliability
If transient filters are added to reduce SETs, then SET propagation is reduced, but power consumption increases and performance decreases
Solution Approach 1:
The transient filter circuit dynamically responds to detected SETs by activating the blocking inverter only when needed. The feedback inverter continuously monitors the output and controls the blocking inverter's operation, allowing the circuit to adapt its filtering strength based on the presence of transients, thereby minimizing impact on normal performance while maintaining protection.
Solution Approach 2:
A feedback inverter is used to monitor the output of the interleaved filter and control the blocking inverter. The feedback mechanism detects when a SET has been blocked and adjusts the circuit operation accordingly, ensuring that the filtering function is activated only when necessary to block transients, thus maintaining high performance during normal operation while providing protection when needed.
3Reliability
If interleaved filter is designed for SOI technology, then SET mitigation is effective, but it is not effective with bulk FinFET technologies
Solution Approach 1:
The interleaved filter design incorporates both a C-gate element and a blocking inverter that work together to provide SET mitigation functionality that is effective across different technology nodes. The blocking inverter component specifically addresses the needs of bulk FinFET technologies by providing an additional layer of protection that compensates for the absence of a buried insulating layer, making the circuit universally applicable to both SOI and bulk FinFET technologies.
Data Source
AI summary
A flip-flop circuit comprises a pass gate, a feedback inverter, and an interleaved filter. The pass gate comprises a clock input and an inverting clock input. The feedback inverter includes a feedback input coupled to both the clock input and the inverting clock input of the pass gate. The interleaved filter comprises a delay circuit including a delay output, a C-gate element, and a blocking inverter. The C-gate element includes a C-gate input and a C-gate output. The C-gate input is coupled to the delay output of the delay circuit and the pass gate, and the C-gate output is coupled to the feedback input of the feedback inverter. The blocking inverter includes a blocking input and a blocking output. The blocking input is coupled to the delay output of the delay circuit, and the blocking output is coupled to the feedback input of the feedback inverter.