Pulse-Based Flip-Flop Setup Time Measurement for Clock Skew Absorption
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Solution Overview
Problem
Accurately measuring setup time in semiconductor IC design is challenging due to the transparency of pulse-based flip-flops, which complicates the absorption of clock skews and time borrowing between stages.
Innovation Solution
A method involving the measurement of first and second delay times from input signal to clock signal and output signal, respectively, with adjustments to determine the setup time, including re-measurement and multiplication factors to ensure minimum sums and specific percentage increases, allowing for accurate representation of transparency characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a pulse-based flip-flop is used to achieve high-speed operation with short setup time, then the operating speed is improved, but the measurement precision of setup time deteriorates due to transparency characteristics
Solution Approach 1:
The patent applies preliminary action by pre-characterizing the pulse-based flip-flop's transparency behavior and clock skew absorption characteristics before actual IC design. Multiple delay measurements are performed in advance to establish setup time parameters, allowing accurate timing analysis without directly measuring during operation. This resolves the contradiction by preparing measurement data beforehand when the system is in a controlled state, avoiding the measurement difficulties that arise during high-speed transparent operation.
Solution Approach 2:
The patent uses an intermediary approach by introducing additional delay elements and measurement circuits that indirectly characterize the setup time. Instead of directly measuring the transparent flip-flop's setup time, the method measures delay times through intermediate paths and uses these measurements to calculate the effective setup time. This intermediary measurement strategy enables precise characterization without being affected by the transparency issue during normal operation.
2Adaptability or versatility
If the transparency characteristic is utilized for clock skew absorption and time borrowing, then the adaptability of the IC design is improved, but the device complexity increases due to multiple measurement and calculation steps
Solution Approach 1:
The patent applies universality by creating a standardized measurement methodology that can be applied to any pulse-based flip-flop in the standard cell library. The same measurement procedure and calculation algorithm work across different flip-flop instances, enabling universal characterization. This reduces the effective complexity by providing a reusable framework rather than requiring custom analysis for each flip-flop, thus maintaining adaptability while managing complexity through standardization.
Solution Approach 2:
The patent uses parameter changes by systematically varying delay parameters during measurement and analyzing how these changes affect the overall timing. By measuring delay times at different parameter settings and establishing mathematical relationships, the method captures the flip-flop's behavior across different operating conditions. This parameter-based approach enables the transparency characteristic to be modeled and utilized for clock skew absorption without requiring complex real-time control logic.
Data Source
AI summary
A method of measuring setup time measures a first delay time from an input signal to a clock signal and a second delay time from the clock signal to an output signal, and determines a setup time using the first delay time and the second delay time. The method of measuring setup time is used in designing a semiconductor IC including a pulse-based flip-flop circuit. The semiconductor IC designed by using the method of measuring setup time absorbs a clock jitter and allows a time borrowing between adjacent pipelines.