Flip-Flop Circuit Width Tuning for Equal Setup Times
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Solution Overview
Problem
Latching circuit designs face inefficiencies due to disparities in rising and falling data setup times caused by unequal slew rates, leading to increased sequential overhead and power consumption, as existing designs are not optimized for equal input transition directions.
Innovation Solution
The method involves generating a library representation of slew rates, creating an initial latching circuit design, optimizing device widths using HSPICE optimization routines to minimize sequential overhead, and recharacterizing the layout to achieve equal setup times for both rising and falling data transitions, thereby reducing sequential overhead and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional latching circuit designs are used with standard device widths, then the circuit structure is simple and easy to manufacture, but the rising and falling data setup times are unequal due to unequal slew rates, leading to increased sequential overhead and power consumption
Solution Approach 1:
The patent applies parameter changes by optimizing device widths (W) of transistors in the latching circuit. Specifically, it adjusts the width ratios between P-channel and N-channel devices in pass-gates and inverters to equalize rising and falling setup times. The optimization involves calculating and adjusting width ratios (e.g., WP/WN) to compensate for unequal slew rates, thereby achieving equal setup times for both rising and falling data transitions without changing the basic circuit topology.
2Speed
If device widths are significantly optimized (more than 15 percent change), then timing optimization improves, but parasitic extraction accuracy decreases and design reliability is compromised
Solution Approach 1:
The patent applies partial action by limiting the device width optimization to within 15 percent of the initial device widths. This constraint ensures that parasitic extraction remains accurate while still achieving sufficient timing optimization. The 15 percent threshold is specifically chosen to maintain the validity of the parasitic extraction model while providing enough design space to equalize rising and falling setup times through controlled adjustments of transistor widths.
3Ease of manufacture
If unequal slew rates are accepted in standard library cells, then library design is simpler, but latching circuit sequential overhead increases
Solution Approach 1:
The patent applies local quality by making the latching circuit locally optimized while keeping the rest of the library standard. Specifically, it adjusts device widths only within the latching circuit components (pass-gates and inverters) to equalize setup times, while maintaining standard library cell characteristics elsewhere. This localized optimization compensates for the unequal slew rates inherent in standard library cells without requiring changes to the entire library design.
Data Source
AI summary
Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be equalized for both rising data transitions and falling data transitions. Large setup times are not required since optimization techniques equalize setup times for both rising and falling data transitions.