Flip-Flop Input Circuit Layout Using Shared MOSFET Gate Strips
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Solution Overview
Problem
The use of flip-flop circuits in semiconductor devices consumes a large area due to the inclusion of dozens of transistors, which is undesirable as semiconductor devices shrink in size.
Innovation Solution
The proposed solution involves an input circuit for a flip-flop that includes P-type and N-type Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) configured as multiplexers, where transistors share gate strips and doping regions to minimize area usage, with a manufacturing method that optimizes the layout to reduce the width of the input circuit to as few as 5 or 6 pitches, thereby saving space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional flip-flop circuits with dozens of transistors are used, then data storage functionality is achieved, but the area occupied is large
Solution Approach 1:
The patent merges multiple transistor functions into shared structures. Specifically, multiple PMOS transistors share a common source region, and multiple NMOS transistors share a common drain region. This consolidation reduces the total number of discrete transistor components while maintaining the data storage functionality, directly addressing the area reduction goal.
Solution Approach 2:
The shared source region serves as the source for multiple PMOS transistors simultaneously, and the shared drain region serves as the drain for multiple NMOS transistors. This multi-functional design allows a single doped region to perform the function of what would traditionally require separate regions for each transistor, thereby reducing overall circuit area.
2Area of stationary object
If the number of transistors in flip-flop circuit is reduced to save area, then area occupation decreases, but device complexity increases
Solution Approach 1:
The gate strips are segmented into distinct sections (first gate strip, second gate strip, third gate strip) that can be independently formed and controlled. This segmentation allows for systematic manufacturing while maintaining the shared region architecture, making the complex layout more manageable through structured division of the gate control elements.
Solution Approach 2:
The patent utilizes vertical stacking and overlapping layouts where gate strips extend over shared doped regions. By arranging components in multiple layers and utilizing vertical space rather than only horizontal expansion, the design achieves area reduction without proportionally increasing lateral layout complexity.
Data Source
AI summary
A manufacturing method of an input circuit of a flip-flop including: depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first and second gate strips, a distance between the second and third gate strips, and a distance between the third and fourth gate strips equal; executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip; executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip; and directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip.