Flip-Flop Input Circuit Layout With Shared MOSFET Gate Strips
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Solution Overview
Problem
The use of flip-flop circuits in semiconductor devices for data storage consumes a large area due to the inclusion of dozens of transistors, which is undesirable as semiconductor devices shrink in size.
Innovation Solution
The proposed solution involves an input circuit for a flip-flop that includes P-type and N-type MOSFETs configured as multiplexers, which share gate strips and doping regions to minimize area usage, with a manufacturing method that involves depositing gate strips and executing cut-off operations to generate gate terminals for PMOS and NMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flip-flop circuits including dozens of transistors are used for data storage, then data storage functionality is achieved, but the area occupied increases significantly
Solution Approach 1:
The patent merges multiple transistor functions into shared structures. Specifically, multiple PMOS transistors share a common first doping region, and multiple NMOS transistors share a common second doping region. This consolidation reduces the total number of discrete transistor components while maintaining the required data storage functionality, directly addressing the area occupation problem.
Solution Approach 2:
The shared doping regions serve multiple functions simultaneously. The first doping region acts as a common source or drain for multiple PMOS transistors, and the second doping region serves the same purpose for multiple NMOS transistors. This multi-functionality reduces the overall component count and area requirement while preserving the flip-flop's data storage capability.
2Area of stationary object
If the number of transistors in flip-flop is reduced to decrease area, then area occupation decreases, but device complexity increases due to shared gate strips and doping regions
Solution Approach 1:
The patent segments the gate strips into distinct first and second gate strips that can be independently controlled. This segmentation allows separate control of the PMOS and NMOS transistor groups while sharing the doping regions, thereby reducing area without excessively increasing complexity. The segmented gates provide clear control signals for each transistor group.
Solution Approach 2:
The patent transitions from a planar arrangement of discrete transistors to a shared doping region architecture that utilizes vertical integration. By having multiple transistors share common source/drain regions in the vertical dimension, the design reduces horizontal area occupation while managing complexity through structured sharing arrangements.
Data Source
AI summary
A manufacturing method of an input circuit of a flip-flop including: depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first and second gate strips, a distance between the second and third gate strips, and a distance between the third and fourth gate strips equal; executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip; executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip; and directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip.