Static Flip-Flop Circuit With Shared Latch Nodes for Zero Setup Time
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Solution Overview
Problem
High-performance synchronous digital systems require flip-flops with low latency and low power consumption, but existing designs often increase power consumption and silicon area by incorporating additional circuit elements to minimize setup time and propagation delay.
Innovation Solution
The flip-flop circuit design incorporates an input propagation unit with stack structures and keeper devices, sharing nodes with the latch to reduce the number of intermediate nodes and eliminate transistors with common functionality, thereby minimizing setup time without increasing power consumption or area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If additional circuit elements are incorporated to minimize setup time and propagation delay, then latency is reduced, but power consumption and silicon area increase
Solution Approach 1:
The patent merges the keeper circuit functionality into the input propagation unit by sharing nodes (top node and bottom node) between these two circuits. This integration eliminates redundant transistors and reduces the total circuit element count while maintaining both the setup time minimization and low power consumption objectives.
Solution Approach 2:
The input propagation unit is designed to serve multiple functions: it acts as both the input propagation path and the keeper circuit. The same transistors and nodes are utilized for both propagating input signals and maintaining stored values, thereby reducing overall circuit complexity and power consumption while achieving low latency.
2Loss of time
If additional circuit elements are incorporated to minimize setup time and propagation delay, then latency is reduced, but silicon area increases
Solution Approach 1:
The patent merges the keeper circuit functionality into the input propagation unit by sharing nodes (top node and bottom node) between these two circuits. This integration eliminates redundant transistors and reduces the total circuit element count while maintaining both the setup time minimization and low power consumption objectives.
3Loss of time
If more circuit elements are used to reduce setup time, then setup time is minimized, but the number of toggling intermediate nodes increases
Solution Approach 1:
The patent merges the keeper circuit functionality into the input propagation unit by sharing nodes (top node and bottom node) between these two circuits. This integration eliminates redundant transistors and reduces the total circuit element count while maintaining both the setup time minimization and low power consumption objectives.
Data Source
AI summary
A latch circuit comprising a tristate driver and a storage feedback loop and having minimal circuit elements is disclosed. The tristate driver and feedback loop couple to internal nodes of a separate latch circuit to reduce total circuit element count by collapsing elements with common functionality into a single circuit element. The latch circuit presents only one transistor gate load to a clock signal, and the output of the separate latch is coupled to the input of the latch circuit to form a flip-flop. The flip-flop generates an output signal based on a received input signal when the clock signal is at second level and stores the received input signal when the clock signal is at first level. The flip-flop is fully static, contention-free, with near-zero setup time, with less circuit elements than prior arts, and can be configured to integrate multi-input logic functions.