Semi-Dynamic Flip-Flop Smart Keeper for Low-Power Robust Timing

The patent implements a semi-dynamic architecture where the flip-flop transitions from fully static to dynamic operation based on clock phase. During the clock high phase, the circuit operates dynamically with precharge and evaluate modes, allowing nodes to be actively driven only when needed. This dynamic behavior eliminates floating nodes during evaluation while reducing overall power consumption compared to fully static designs that must continuously drive all nodes.

The flip-flop is divided into distinct functional blocks: precharge circuit, evaluation circuit, master latch, and slave latch. Each segment has specific activation timing controlled by clock phases and evaluation signals. This segmentation allows different parts of the circuit to be in different operational states simultaneously, preventing race conditions between conflicting signal paths while maintaining robust node driving only where and when needed.

The precharge circuit activates before the evaluation phase to pre-establish voltage levels on critical nodes. By preliminarily charging capacitive nodes to known states before data evaluation begins, the circuit eliminates uncertainty and prevents race conditions. This preliminary action ensures that when evaluation starts, all nodes are in predictable states, allowing faster operation without compromising reliability.

The evaluation signal acts as an intermediary control that coordinates between the precharge circuit, evaluation circuit, and latch elements. This intermediary signal ensures proper sequencing: precharge completes before evaluation starts, and evaluation completes before latch transparency changes. This mediation eliminates direct race conditions between conflicting signal paths while enabling high-speed operation through optimized timing.