Flip-Flop Latch Wiring for Soft Error Resistance

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Solution Overview

Problem

Conventional flip-flop circuits face challenges in suppressing overheads of circuit area, delay time, and power consumption while maintaining effective soft error resistance, especially in semiconductor integrated circuit devices used in vehicles, where radiation-induced soft errors can invert memory element values.

Innovation Solution

The proposed flip-flop circuit design includes a master latch and slave latch configuration with specific NMOS and PMOS transistor arrangements and additional wiring connections to enhance the driving force of tri-state inverters, improving radiation resistance and reducing overheads by increasing the critical charge amount and current flow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a redundant flip-flop circuit with tripled flip-flop circuits and majority decision circuit is used, then soft error resistance is improved, but circuit area, delay time, and power consumption significantly increase

Engineering Contradiction:

Improvesoft error resistanceVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the functions of multiple flip-flop circuits and majority decision logic into a single integrated flip-flop structure. The master latch and slave latch share common transistors and wiring, combining what would traditionally be separate redundant circuits into one unified design that achieves soft error resistance without requiring tripled circuit instances.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The flip-flop circuit is designed to perform multiple functions within a single structure: it provides normal flip-flop operation, soft error detection, and soft error correction capabilities all in one circuit. The master latch and slave latch work together to both store data and detect/correct soft errors, eliminating the need for separate dedicated error correction circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If a redundant flip-flop circuit with tripled flip-flop circuits and majority decision circuit is used, then soft error resistance is improved, but delay time significantly increases

Engineering Contradiction:

Improvesoft error resistanceVSAvoiddelay time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The circuit performs preliminary soft error detection and correction within the normal operation flow. The master latch continuously monitors and corrects soft errors in the slave latch during regular flip-flop operation, rather than requiring separate correction cycles or additional time-consuming majority voting operations after the fact.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If a redundant flip-flop circuit with tripled flip-flop circuits and majority decision circuit is used, then soft error resistance is improved, but power consumption significantly increases

Engineering Contradiction:

Improvesoft error resistanceVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Inventive Principle:

Principle #25Self-service

4Area of stationary object

If conventional flip-flop circuit with majority decision based on master latch and two slave latch circuits is used, then overheads of circuit area, delay time, and power consumption are suppressed, but soft errors can be detected and corrected only in clock stop state

Engineering Contradiction:

Improvecircuit areaVSAvoidsoft error correction capability

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The soft error detection and correction operates continuously during normal clocked operation. The master latch continuously monitors the slave latch and performs correction whenever needed, rather than stopping the clock to perform correction as in conventional designs. This maintains both the compact circuit area and continuous soft error protection.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS12009817B2Flip-flop circuit, semiconductor integrated circuit device, and vehicle

Publication Date: 2024.06.11 ROHM CO LTD

AI summary

A flip-flop circuit includes master latch including a first inverter and a first tri-state inverter, wherein the first tri-state inverter includes a first NMOS transistor and a first PMOS transistor; a slave latch including a second inverter and a second tri-state inverter, wherein the second tri-state inverter includes a second PMOS transistor and a second NMOS transistor; and at least one of a first wiring configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor and a second wiring configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor.