Flip-Flop Standard Cell Layout Using Single Clock Signal
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Solution Overview
Problem
Current integrated circuit design methods require complex layouts and multiple clock signals for flip-flop circuits, leading to increased complexity and power consumption, especially when using CMOS transmission gates.
Innovation Solution
A standard cell layout for flip-flop circuits that uses only one clock signal and eliminates CMOS transmission gates, employing FinFET transistors and optimized wiring configurations to reduce the number of electrically conductive wirings and enhance design freedom.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS transmission gates are used in flip-flop circuits, then the circuit can achieve proper signal transmission and clocking functionality, but the layout complexity and power consumption increase significantly
Solution Approach 1:
The patent extracts and eliminates the CMOS transmission gate component from the flip-flop circuit. By removing this complex component, the circuit achieves the same functionality using simpler logic gates and wiring, directly reducing layout complexity while maintaining signal transmission reliability
Solution Approach 2:
The patent substitutes the mechanical/transmission gate-based signal switching mechanism with a logic gate-based computational approach. Instead of using physical transmission gates controlled by clock signals, the invention uses combinatorial logic gates (AND, OR, NOT) to achieve the same timing and signal routing functions
2Reliability
If CMOS transmission gates are used in flip-flop circuits, then the circuit can achieve proper signal transmission and clocking functionality, but the power consumption increases
Solution Approach 1:
The patent extracts and eliminates the CMOS transmission gate component from the flip-flop circuit. By removing this complex component, the circuit achieves the same functionality using simpler logic gates and wiring, directly reducing layout complexity while maintaining signal transmission reliability
Solution Approach 2:
The patent substitutes the mechanical/transmission gate-based signal switching mechanism with a logic gate-based computational approach. Instead of using physical transmission gates controlled by clock signals, the invention uses combinatorial logic gates (AND, OR, NOT) to achieve the same timing and signal routing functions
3Reliability
If multiple clock signals are used in flip-flop circuits, then the circuit can achieve proper timing and signal synchronization, but the wiring complexity and design freedom decrease
Solution Approach 1:
The patent makes the single clock signal perform multiple functions that previously required separate clock signals. The same clock signal is used for both timing control and signal synchronization across different circuit stages, eliminating the need for separate clock phasing while maintaining proper synchronization
Solution Approach 2:
The patent substitutes the mechanical/transmission gate-based signal switching mechanism with a logic gate-based computational approach. Instead of using physical transmission gates controlled by clock signals, the invention uses combinatorial logic gates (AND, OR, NOT) to achieve the same timing and signal routing functions
4Productivity
If standard cell layouts are reduced in height, then more transistors can be integrated in the circuit, but the wiring and signal routing become more constrained
Solution Approach 1:
The patent resolves the routing constraint by changing the dimensional arrangement of components. Instead of forcing all connections to occur within the constrained horizontal plane of a narrow cell, the design uses vertical stacking and multi-layer interconnect approaches, allowing signals to route in multiple dimensions and maintaining routing flexibility despite reduced cell height
Data Source
AI summary
A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.