Flip-Flop Latch Circuit for Fast Thread State Swapping

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Solution Overview

Problem

In multi-threading processing systems, switching between threads often results in unacceptable delays or interruptions during logic built-in self-test (LBIST) operations due to time-consuming thread switching processes.

Innovation Solution

The implementation of an enhanced flip-flop circuit with a feedback latch, master latch, and slave latch, along with additional components to enable fast data swapping and a control signal for swap operations, allowing for efficient switching between threads and enabling faster checkpoint/restore capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional thread switching is used in multi-threading processing systems, then multiple threads can be executed, but unacceptable delays or interruptions occur during LBIST operations

Engineering Contradiction:
Improvethread switching speedVSAvoidthread switching delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by pre-storing thread state information in dedicated latch circuits (master latch, slave latch, and feedback latch) before switching is needed. The feedback latch specifically holds previous state information that can be rapidly restored, eliminating the need for time-consuming state reconstruction during thread switching. This pre-positioning of state data enables instantaneous thread context restoration.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the thread state storage function into multiple specialized latch circuits: master latch for current state, slave latch for intermediate state, and feedback latch for previous state. This segmentation allows parallel access and independent manipulation of different state components, enabling fast switching by selectively transferring data between segmented storage elements rather than processing the entire thread state as a single unit.

Inventive Principle:
Principle #1Segmentation

2Reliability

If LBIST operations are performed on a processor, then testing functionality is achieved, but normal functional operation is interrupted

Engineering Contradiction:
Improvetesting capabilityVSAvoidnormal operation continuity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent creates a copy of the thread state in the feedback latch before LBIST operations begin. This copied state can be rapidly restored after testing completes, allowing the processor to switch back to normal operational threads quickly. The copying mechanism enables independent testing execution without permanent disruption to the normal operational thread pool.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent implements discarding and recovering by temporarily suspending normal thread execution during LBIST operations and then rapidly recovering the previous thread state from the feedback latch after testing completes. The controlled discarding of normal operation (to perform testing) followed by quick recovery minimizes the impact on overall productivity while ensuring reliability through comprehensive testing.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS8631292B2Multi-threading flip-flop circuit
Publication Date: 2014.01.14 NXP USA INC
  • US8631292B2 patent drawing
  • US8631292B2 patent drawing
  • US8631292B2 patent drawing

AI summary

A flip-flop circuit includes a master latch, a master/slave gate, a slave latch, a slave gate, a feedback latch, and a master gate. The master latch has an input and an output. The master/slave gate has an input coupled to the output of the master latch and an output. The slave latch has input coupled to the output of the master/slave gate and an output. The slave gate has input coupled to the output of the slave latch and an output. The has an input coupled to the output of the slave gate and an output. The master gate has an input coupled to the output of the feedback latch and an output coupled to the input of the master latch.