Flip-Flop Circuit Threshold Voltage Tuning for Low-Speed Signal Holding
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Solution Overview
Problem
Flip-flop circuits face challenges in maintaining the potential of a node in a floating state at low speeds due to leakage currents, leading to incorrect signal holding, which increases circuit size and current consumption.
Innovation Solution
A flip-flop circuit configuration with N gate circuits, where the output signal from the (N−1)th gate serves as the input for the N-th gate, utilizing two groups of MOS transistors with different threshold voltages to manage the potential of the output signal node, with the first group having higher threshold voltages to suppress leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If MOS transistors are used in a floating state to hold potential in a flip-flop circuit, then the circuit can operate at high speed, but at low speed the leakage current causes incorrect potential holding
Solution Approach 1:
The patent applies local quality by differentiating the threshold voltages of MOS transistors based on their functional roles. Specifically, the first MOS transistor (in the OFF state during potential holding) has a higher threshold voltage to minimize leakage current, while the second MOS transistor (in the ON state) has a lower threshold voltage to ensure strong signal transmission. This localized optimization of transistor characteristics resolves the contradiction between high-speed operation and reliable potential holding at low speeds.
2Reliability
If a level fixing unit including a delay circuit is provided to fix the level of a node in the floating state, then potential holding reliability is improved, but the circuit size and current consumption increase
Solution Approach 1:
The patent extracts and eliminates the unnecessary level fixing unit (delay circuit) from the flip-flop circuit. By doing so, it reduces circuit size and current consumption. The reliability of potential holding is maintained not through additional circuits but through the optimized threshold voltage design of the MOS transistors, particularly the first MOS transistor with higher threshold voltage that suppresses leakage current in the floating state.
3Reliability
If a level fixing unit is provided to fix the level of a node in the floating state, then potential holding reliability is improved, but current consumption increases
Solution Approach 1:
The patent removes the level fixing unit from the circuit, thereby eliminating its current consumption. The reliability of potential holding is achieved through the inherent properties of the MOS transistors with differentiated threshold voltages, specifically the first MOS transistor with higher threshold voltage that minimizes leakage current during the floating state, without requiring additional active circuits.
Solution Approach 2:
The flip-flop circuit achieves potential holding reliability through the self-service mechanism of the MOS transistors themselves. The first MOS transistor, with its higher threshold voltage, automatically suppresses leakage current and maintains the floating state potential without external intervention or additional circuits. This self-regulating property eliminates the need for the level fixing unit and its associated current consumption.
Data Source
AI summary
A flip-flop circuit includes gate circuits of which the number is N being an integer of 3 or more, and in which an output signal from the (N−1)th gate circuit is used as an input signal of the N-th gate circuit, the gate circuit being configured to output the output signal in response to a clock signal and the input signal. The N gate circuits include a first MOS transistor group including MOS transistors which are in an OFF state when a potential of an output signal node that outputs the output signal is held, and a second MOS transistor group including MOS transistors which are in an ON state when the potential of the output signal node is held. A threshold voltage of at least one MOS transistor in the first MOS transistor group is higher than a threshold voltage of at least one MOS transistor in the second MOS transistor group.