Flip-Flop Vulnerability Categorization for Circuit Reliability
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Solution Overview
Problem
Existing data processing circuit reliability analysis methods fail to accurately assess the vulnerability of flip-flops (flops) to transient errors, as they do not consider the actual utilization and inter-relationships of flops during program execution, leading to an incomplete view of circuit reliability.
Innovation Solution
An apparatus and method that categorize flops as vulnerable, conditionally vulnerable, or isolated based on their vulnerability to transient errors, determining the set of currently vulnerable flops per processing cycle, and calculating instantaneous and aggregate failure probabilities using simulation and formal analysis tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional activity-based analysis is used to assess flop vulnerability, then the analysis is simple and fast, but the reliability assessment is inaccurate
Solution Approach 1:
The patent segments flops into three distinct vulnerability categories (vulnerable, conditionally vulnerable, isolated) based on their structural relationships and execution contexts. This segmentation enables precise reliability assessment by analyzing each category's specific failure modes and propagation characteristics, rather than treating all flops uniformly as in traditional activity-based analysis.
Solution Approach 2:
The patent performs preliminary vulnerability categorization of flops before reliability analysis by examining structural relationships and execution traces. This preliminary classification establishes a foundation for more accurate subsequent analysis, identifying which flops require detailed vulnerability assessment and which can be excluded, thereby improving overall assessment accuracy without proportionally increasing complexity.
2Reliability
If comprehensive vulnerability analysis is performed on all flops, then reliability assessment improves, but computational complexity increases
Solution Approach 1:
The patent applies local quality by differentiating vulnerability characteristics across different flop locations and contexts within the circuit. Each flop is analyzed according to its specific structural relationships, execution frequency, and data flow context, allowing comprehensive reliability assessment focused on critical regions while reducing unnecessary analysis of isolated or low-risk flops.
Solution Approach 2:
The patent performs partial vulnerability analysis by focusing computational resources on flops that are actually executed and contribute to circuit output, rather than analyzing all flops equally. The methodology identifies and excludes isolated flops that cannot affect circuit behavior, performing detailed analysis only on vulnerable and conditionally vulnerable flops, thus maintaining comprehensive assessment where needed while improving overall efficiency.
3Measurement precision
If fault injection methods are used to test vulnerability, then actual failure modes are observed, but the process is time-consuming and resource-intensive
Solution Approach 1:
The patent performs preliminary vulnerability categorization and failure mode identification through static analysis and execution trace examination, before actual fault injection testing. By pre-identifying vulnerable flops and their potential failure modes, the methodology reduces the scope and duration of subsequent fault injection tests, focusing resources only on critical paths and vulnerable components rather than exhaustive testing of all circuit elements.
Solution Approach 2:
The patent creates a virtual model of the circuit's vulnerability characteristics through static analysis and execution profiling, which serves as a surrogate for extensive physical fault injection testing. This virtual vulnerability model predicts failure modes and propagation paths, reducing the need for time-consuming physical fault injection while maintaining accurate failure mode detection capability.
Data Source
AI summary
An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.