Flipchip Leadframe Packaging with Thin Encapsulant
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Solution Overview
Problem
The miniaturization of semiconductor packages poses challenges in accommodating small flip chips on leadframes, particularly in attaching multiple flip chips and stacking different types of chips, while maintaining low cost, high yield, reliability, and testability.
Innovation Solution
The integrated circuit packaging system involves forming a leadframe with leads and a paddle, molding a thin encapsulant between the leads and paddle, applying a non-conductive layer, and creating conductive traces on the leads, encapsulant, and non-conductive layer to facilitate the attachment and stacking of flip chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the leadframe size is reduced to accommodate miniaturization, then the package size decreases, but the difficulty of attaching small flip chips increases
Solution Approach 1:
The patent applies preliminary action by forming a solder resist pattern and conductive traces on the leadframe before attaching the flip chip. This pre-preparation of electrical connections and protective layers facilitates easier and more reliable attachment of small flip chips to miniaturized leadframes, resolving the contradiction between reduced package size and manufacturing difficulty.
2Adaptability or versatility
If multiple flip chips are attached to a leadframe, then functionality increases, but the manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the leadframe into multiple distinct attachment areas, each with its own solder resist pattern and conductive trace configuration. This allows multiple flip chips to be attached in an organized manner with dedicated electrical connections for each chip, thereby increasing functionality while managing manufacturing complexity through systematic segmentation of the attachment process.
3Quantity of substance
If different types of chips are stacked onto a flip chip, then integration density increases, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies the intermediary principle by using a solder resist pattern as a mediating layer between the leadframe and the stacked chips. This solder resist pattern provides precise alignment features and defines specific attachment locations, enabling different types of chips to be stacked with high precision. The conductive traces also serve as intermediaries, providing clear electrical connection pathways that facilitate precise positioning and connection of multiple chip types.
Data Source
AI summary
An integrated circuit packaging system and method of manufacture thereof includes: leads and a paddle; a first encapsulant molded between the leads and the paddle, the first encapsulant thinner than the leads; a non-conductive layer over the paddle; and conductive traces directly on the leads, the first encapsulant, and the non-conductive layer.