Flip-Flop Clock Gating with Reduced Clock Transitions
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Solution Overview
Problem
Flip-flops in integrated circuits consume significant power, especially when numerous, which is undesirable in mobile applications where reducing active power consumption is crucial.
Innovation Solution
A flip-flop device with a gating circuit that generates lower-activity clock signals (clk_nand and clk_nor) from a full-activity input clock signal (CP), reducing signal transitions and thereby lowering power consumption by controlling the operation modes through a selecting circuit, master circuit, slave writing circuit, and slave circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full-activity clock signal is used to control the flip-flop, then the flip-flop can operate correctly and maintain reliability, but the power consumption increases significantly
Solution Approach 1:
The patent applies dynamics by making the clock signal activity adaptive rather than static. The gating circuit dynamically adjusts the clock signal transitions based on the actual data changes in the flip-flop, allowing the system to operate reliably when needed while reducing activity when data remains unchanged, thus resolving the contradiction between reliability and power consumption
Solution Approach 2:
The patent changes the parameter of clock signal activity from full-activity to variable activity. By using gating circuits to control clock transitions based on data change detection, the system maintains full-activity clocking when reliability is critical while reducing to lower-activity mode when data is stable, effectively addressing the power-consumption-reliability trade-off
2Adaptability or versatility
If numerous flip-flops are applied in an integrated circuit, then the functionality and storage capacity increase, but the total power consumption is dominated by the flip-flops
Solution Approach 1:
The patent segments the clock distribution system by introducing gating circuits at each flip-flop stage. This allows independent control of clock signals to different flip-flops based on their individual data change needs, enabling the system to maintain high storage capacity while reducing overall power consumption by activating only the necessary segments
Solution Approach 2:
The patent applies partial action by providing clock signals to only those flip-flops that require updates based on data changes. Instead of uniformly clocking all flip-flops (excessive action), the gating circuits enable selective clocking, maintaining storage functionality while avoiding unnecessary power consumption from idle flip-flops
Data Source
AI summary
An integrated circuit includes: a flip-flop circuit arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode; and a gating circuit coupled to the flip-flop circuit, for generating the first clock signal and the second clock signal according to the master signal and an input clock signal; wherein a first signal transition number of the first clock signal and a second signal transition number of the second clock signal are not greater than a third signal transition number of the input clock signal during the writing mode and the storing mode.