Dual-Port Slave Latch Flip-Flop for External Data Updates
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Solution Overview
Problem
Non-volatile logic circuits face challenges in updating sequential elements like flip-flops from external sources without significantly slowing down operations, especially in portable devices where power efficiency and data retention are crucial.
Innovation Solution
A flip-flop circuit design incorporating a 2-input multiplexer, master latch, transfer gate, and dual-port slave latch with a tri-state inverter, allowing for external data insertion without affecting the critical timing path, enabling efficient updating and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile logic circuits are implemented to allow updating of sequential elements from external sources, then data retention capability is improved, but the operation speed of sequential elements is significantly slowed down
Solution Approach 1:
The flip-flop is divided into two independent latches: a master latch for normal high-speed operation and a slave latch for non-volatile data storage. The master latch operates at full speed using conventional logic, while the slave latch handles external data updates through a dedicated dual-port interface. This segmentation allows both functions to operate independently without interfering with each other's performance.
Solution Approach 2:
A dual-port slave latch acts as an intermediary between external non-volatile memory and the master latch. It provides a dedicated data path for external updates that does not interfere with the critical timing path of normal operations. The slave latch buffers and conditionally transfers data to the master latch only when update operations are performed, maintaining normal operation speed while enabling data retention.
2Adaptability or versatility
If a dual-port slave latch is added to enable external data insertion, then adaptability is improved, but device complexity increases
Solution Approach 1:
The slave latch is designed with dual ports that serve multiple functions: Port 1 handles external data from non-volatile memory, while Port 2 handles internal data from the master latch. The same hardware structure supports both normal flip-flop operation and non-volatile data updates, eliminating the need for separate dedicated circuits for each function and reducing overall complexity.
Solution Approach 2:
The update control logic, tri-state inverters, and data transfer mechanisms are merged into the existing latch structure. The slave latch combines external data input paths with internal feedback paths in a unified circuit design, sharing common control signals and logic gates to manage both data sources without requiring entirely separate control circuits.
Data Source
AI summary
In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.