Pulsed Latch Conversion With Timing-Balanced Clock Networks
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Solution Overview
Problem
Integrated circuits consume significant dynamic power due to the use of edge-triggered flip-flops, which can be reduced by replacing them with pulsed latches, but existing techniques face challenges in designing and optimizing circuit designs for effective replacement.
Innovation Solution
A circuit design system and methodology that automatically modifies the circuit design to replace edge-triggered flip-flops with pulsed latches, using pulse generators and delay cells to maintain timing and power efficiency, while optimizing skew and slew parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If edge-triggered flip-flops are used to propagate data synchronously with a periodic clock signal, then data propagation reliability is improved, but dynamic power consumption increases
Solution Approach 1:
The patent applies periodic action by using pulsed latches triggered by periodic pulse signals instead of continuous periodic clock signals. The pulse generators create narrow periodic pulses that trigger the latches, reducing the time during which switching occurs and thereby reducing dynamic power consumption while maintaining reliable data propagation at the required timing intervals
2Stability of the object's composition
If a clock tree network is used to route clock signals to flip-flops, then synchronous data propagation is improved, but dynamic power consumption increases
Solution Approach 1:
The patent replaces the periodic clock signal distribution network with pulse-triggered latches that use narrow periodic pulses. This reduces the duration of switching activity in the clock network, thereby reducing dynamic power consumption while maintaining synchronous data propagation through the pulse-triggered latch mechanism
Solution Approach 2:
The patent changes the clock signal parameters by transitioning from wide periodic clock cycles to narrow periodic pulses. This parameter change reduces the capacitance charging/discharging cycles in the clock network, thereby reducing dynamic power consumption while maintaining the timing synchronization required for reliable data propagation
3Use of energy by moving object
If pulsed latches are used to reduce dynamic power consumption, then energy efficiency is improved, but design complexity increases
Solution Approach 1:
The patent introduces pulse generators as intermediary components that convert standard periodic clock signals into narrow periodic pulses suitable for triggering latches. This intermediary element simplifies the overall design by providing a systematic method to generate the required pulse signals without requiring complex manual timing analysis and optimization for each latch location
4Use of energy by moving object
If multiple pulse generators are added to replace flip-flops with pulsed latches, then dynamic power consumption is reduced, but clock network complexity increases
Solution Approach 1:
The patent merges multiple pulse generators by allowing them to share common clock sources and control signals. This consolidation reduces the overall complexity of the clock network while still providing the necessary pulse-triggered functionality across multiple latch locations, thereby reducing dynamic power consumption without proportionally increasing network complexity
Data Source
AI summary
A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.