Reset Assertion Detection via Flip-Flop Pattern Checking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Digital electronic circuits face attacks where the reset signal is prevented from being asserted, allowing unintended features to be enabled due to flip flops powering up in an undetermined state, leading to a 50% chance of incorrect initialization.
Innovation Solution
A dedicated reset detection circuitry system that monitors the assertion of the reset signal and outputs a confirmatory signal, which can trigger a reset signal if not asserted, using a group of flip flops configured to output a predetermined pattern when reset is active, and a comparator to verify this pattern, ensuring correct initialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reset signal is not asserted during power up, then flip flops may power up in an undetermined state with 50% chance of incorrect initialization, but adding reset detection circuitry increases device complexity
Solution Approach 1:
The reset detection circuitry proactively monitors the reset signal assertion status during power-up before features can be enabled. By detecting whether the reset signal was properly asserted in advance, the system can prevent incorrect initialization of features before the attack takes effect, rather than reacting after the fact.
Solution Approach 2:
The reset detection circuitry continuously monitors the reset signal and provides feedback about its assertion status. This feedback mechanism allows the system to verify proper reset operation and trigger corrective actions if the reset signal is prevented from being asserted, creating a closed-loop control system that enhances initialization reliability.
2Reliability
If reset detection circuitry is added to monitor reset signal assertion, then unauthorized feature enabling is prevented, but manufacturing cost increases
Solution Approach 1:
The reset detection circuitry is fully integrated into the chip and autonomously monitors the reset signal assertion status without requiring external monitoring equipment or additional manufacturing processes. The circuit self-verify the reset operation and automatically trigger corrective actions, eliminating the need for specialized external testing equipment and reducing manufacturing complexity.
Solution Approach 2:
The reset detection circuitry serves multiple functions: it monitors reset signal assertion, detects reset attacks, verifies flip flop initialization, and triggers corrective actions. This multi-functional approach consolidates security features into a single integrated circuit block, reducing overall chip complexity and manufacturing cost compared to implementing separate dedicated circuits for each function.
3Adaptability or versatility
If the reset pin is lifted or overdriven to prevent reset assertion, then features can be unauthorizedly enabled, but this creates detectable electrical disturbances
Solution Approach 1:
The reset detection circuitry converts the harmful electrical disturbances caused by reset attacks (such as lifting or overdriving the reset pin) into detectable signals. By monitoring these disturbances, the system can identify when an attack is occurring and trigger corrective actions, transforming the attacker's harmful actions into beneficial detection opportunities.
Solution Approach 2:
The reset detection circuitry prepares anti-countermeasures in advance by continuously monitoring the reset signal assertion status and electrical characteristics. When disturbances indicating a reset attack are detected, the system has already positioned itself to immediately trigger corrective actions such as forcing flip flops to their initial state, preventing the unauthorized feature enabling before it can take effect.
Data Source
AI summary
A system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.