Selective Latch Hardening in Flip-Flops for Lower SER Penalty
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Solution Overview
Problem
Existing methods for reducing Soft Error Rate (SER) in sequential elements like latches and flip-flops outside memory arrays are inefficient due to high area, power, and timing penalties, and current error correction techniques are not applicable to sequential elements.
Innovation Solution
Implementing hardened latch circuitry in only one of the master or slave latches of a flip-flop, rather than both, to achieve high SER protection with lower power, timing, and area penalties, while maintaining similar SER protection levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardened latch circuitry is implemented in both master and slave latches of a flip-flop, then SER protection is improved, but area, power, and timing penalties increase significantly
Solution Approach 1:
The patent applies local quality by implementing hardened latch circuitry selectively in only one of the master or slave latches, rather than uniformly in both. This localized approach provides SER protection where most needed while avoiding redundant hardening in the other latch, thereby reducing area penalty while maintaining adequate reliability
Solution Approach 2:
The patent applies partial action by implementing hardening in only one latch instead of both, achieving sufficient SER protection without the excessive resource consumption of full hardening. This partial approach balances reliability improvement with acceptable area, power, and timing overhead
2Reliability
If hardened latch circuitry is implemented in both master and slave latches of a flip-flop, then SER protection is improved, but power consumption increases significantly
Solution Approach 1:
The patent reduces power penalty by applying hardening locally to only one latch, thereby eliminating the redundant power consumption associated with hardening both latches while maintaining sufficient SER protection through the single hardened latch
Solution Approach 2:
The patent applies partial hardening action to reduce power consumption, implementing protection in only one latch rather than both, achieving an optimal balance between SER protection and power efficiency
3Reliability
If hardened latch circuitry is implemented in both master and slave latches of a flip-flop, then SER protection is improved, but timing performance deteriorates
Solution Approach 1:
The patent mitigates timing penalty by localizing hardening to one latch, reducing the cumulative timing overhead that would result from hardening both latches while maintaining adequate SER protection
Solution Approach 2:
The patent applies partial hardening to optimize timing performance, implementing protection in only one latch to minimize timing penalties while achieving sufficient SER protection levels
4Reliability
If traditional error correction techniques like ECC or parity protection are applied to sequential elements, then SER protection is improved, but device complexity increases
Solution Approach 1:
The patent extracts the error protection function from complex external schemes like ECC or parity and integrates it directly into the latch structure itself, eliminating the need for separate error correction circuits and thereby reducing device complexity while maintaining SER protection
Solution Approach 2:
The hardened latch circuitry performs multiple functions: it provides the basic latch functionality while simultaneously providing SER protection, eliminating the need for separate error correction components and reducing overall device complexity
Data Source
AI summary
Described is soft error tolerant flip-flop which comprises hardened sequential elements to reduce latch soft error rate. The flip-flop may include a master latch; and a slave latch coupled to the master latch, wherein only one of the master or slave latch of the flip-flop comprises hardened latch circuitry. For example, only the master latch comprises the hardened latch circuitry.