Flipped-Gate Transistor Bandgap Circuit for Temperature Stability
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Solution Overview
Problem
Existing reference voltage generation circuits, such as bandgap circuits, face challenges in achieving temperature independence and stability due to non-linearities, particularly in integrated circuits where discrete components like resistors and capacitors are not feasible or efficient.
Innovation Solution
A bandgap circuit utilizing flipped-gate transistors and polysilicon implants in NMOS transistors generates a reference voltage by summing and differencing gate-source voltages, with current sources and trim devices to compensate for both first and second-order temperature-related non-linearities, eliminating the need for discrete components like resistors and capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete components like resistors and capacitors are used in bandgap circuits, then temperature compensation can be achieved, but device complexity and integration difficulty increase
Solution Approach 1:
The patent extracts the temperature compensation function from discrete resistors and capacitors and implements it using only MOS transistors with opposite polarity gate terminals. This removes the need for discrete components while maintaining the temperature compensation capability through the unique transistor configuration where one transistor has a gate terminal of opposite polarity to exploit threshold voltage temperature characteristics.
Solution Approach 2:
The MOS transistors with opposite polarity gate terminals serve multiple functions: they provide both the reference voltage generation and the temperature compensation mechanisms within the same component. This multi-functionality eliminates the need for separate discrete temperature compensation components, reducing overall device complexity while maintaining reliability.
2Productivity
If MOS transistors are used instead of BJTs in bandgap circuits, then integration efficiency improves, but achieving temperature independence becomes more difficult
Solution Approach 1:
The patent introduces asymmetry by using MOS transistors with opposite polarity gate terminals instead of conventional matched transistor pairs. This asymmetric configuration exploits the different temperature coefficients of transistors with opposite polarity gates to achieve temperature compensation, enabling MOS-based integration while maintaining temperature independence that was traditionally difficult to achieve with MOS devices.
Solution Approach 2:
The patent changes the critical parameter of gate terminal polarity to achieve temperature compensation. By utilizing transistors with opposite polarity gate terminals, the circuit exploits the contrasting temperature dependencies of their threshold voltages to compensate for temperature variations, thereby achieving temperature independence in an integrated MOS implementation.
3Reliability
If flipped-gate transistors are used to compensate for temperature non-linearities, then reference voltage stability improves, but device complexity increases
Solution Approach 1:
The patent uses a copy of the transistor structure with opposite polarity gate terminals to mirror and counteract the temperature non-linearities. By creating a complementary transistor configuration that replicates the electrical characteristics but with opposite polarity, the circuit can subtract the non-linear temperature effects, achieving stable reference voltage without complex external compensation networks.
Data Source
AI summary
A reference voltage generation circuit (or bandgap circuit) having a flipped-gate transistor is disclosed. A bandgap circuit according to the disclosure includes first, second, third and fourth transistors. The first transistor is a flipped-gate transistor having a gate terminal of an opposite polarity (e.g., an n-channel metal oxide semiconductor, or NMOS, transistor having a gate terminal with a p-type polysilicon implant). The second third and fourth transistors have a corresponding type polysilicon implants (e.g., NMOS transistors having respective gate terminals with an n-type polysilicon implant). The circuit is configured to generate a reference voltage equal to a sum of gate-source voltages of the first and third transistors, minus respective gate-source voltages of the second and fourth transistors.