Flipped-Gate MOS UVLO Circuit for Noise-Resistant Voltage Threshold Detection
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Solution Overview
Problem
Existing under-voltage lockout (UVLO) circuits for low power electronic devices have large die area and high current consumption, and are prone to kick-back noise affecting the reference voltage source, leading to unpredictable device behavior due to undefined voltage regions.
Innovation Solution
A UVLO circuit utilizing a non-differential comparator with a flipped gate transistor and a reference current source, along with a voltage divider and inverter buffer, to determine if the power supply voltage has risen or fallen to functional or non-functional thresholds, while minimizing noise impact on the reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional UVLO circuit is used, then the device can detect voltage thresholds, but the die area is large and current consumption is high
Solution Approach 1:
The patent combines the comparator and voltage divider functions into a single integrated circuit block, reducing the overall die area. The flipped-gate MOS transistor structure merges multiple functions (comparator, reference generation, and switching) into one compact unit, eliminating the need for separate discrete components that would increase area.
Solution Approach 2:
The patent uses flipped-gate MOS transistors which have different electrical characteristics (threshold voltage, transconductance) compared to conventional MOS transistors. This parameter change enables the circuit to achieve the same voltage detection function with fewer components and smaller area, while maintaining the required detection precision.
2Reliability
If a traditional UVLO circuit is used, then the device can detect voltage thresholds, but current consumption is high
Solution Approach 1:
The UVLO circuit is designed to be fully operational only during voltage threshold detection events rather than continuously. The flipped-gate MOS transistor structure enables the circuit to enter low-power states when voltage monitoring is not actively required, reducing average current consumption while maintaining detection capability when needed.
Solution Approach 2:
The use of flipped-gate MOS transistors with modified electrical parameters (lower threshold voltage, reduced leakage current) directly reduces the current consumption of the UVLO circuit while maintaining its voltage detection functionality, addressing the energy efficiency requirement for wearable devices.
3Device complexity
If a simple voltage comparison circuit is used, then the circuit is simple, but kick-back noise affects the reference voltage source
Solution Approach 1:
The patent introduces an intermediary buffering stage between the voltage comparison node and the reference voltage source. This buffer acts as a mediator that isolates the reference source from noise generated during switching operations, preventing kick-back effects while maintaining circuit simplicity through the use of standard MOS transistor configurations.
4Ease of manufacture
If conventional MOS transistors are used, then the circuit is easy to manufacture, but the circuit occupies large area and consumes high current
Solution Approach 1:
The patent employs flipped-gate MOS transistors which are manufactured using standard CMOS fabrication processes (maintaining ease of manufacture) but with modified gate structure parameters. The flipped gate configuration changes the electrical characteristics to reduce area and current consumption while remaining compatible with conventional manufacturing techniques.
Data Source
AI summary
An under-voltage lockout (UVLO) circuit configured for indicating that an electronic device may be enabled and disabled based on threshold levels of a power supply voltage. The UVLO circuit has a non-differential comparator configured to have a fixed threshold voltage. A voltage divider having a first terminal connected to the power supply voltage and configured to adapt a compare signal applied to the non-differential comparator to be proportional the power supply voltage such that a desired threshold voltage for the power supply voltage causes the non-differential comparator to change its output state. The UVLO circuit has a hysteresis controller configured for adjusting the compare voltage such that the power supply voltage has at least two threshold voltages to cause the non-differential comparator to change states. The non-differential comparator comprises a flipped gate transistor with a gate-to-source threshold greater than a normally gated transistor.