3D Circuit Transistors with Flipped Gate for Thermal Management
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Solution Overview
Problem
The production of 3D integrated circuits with transistors distributed over several levels faces challenges such as degradation of lower level materials and inter-level connection issues due to high temperature heat treatments, and the need for high-quality gate dielectrics that require thermal budgets exceeding 550°C, while also dealing with the complexity of interconnection size and density.
Innovation Solution
A method is introduced where the gate pattern of upper level transistors is formed first, allowing for the integration of a thermal oxide gate dielectric without subjecting the lower levels to high temperatures, and including localized thinning and oxidation of the semiconducting layer to facilitate channel control and reduce thermal budget, while also reducing inter-level connection size through specific gate and contact pad arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high temperature heat treatment is applied to produce upper level transistors, then good quality gate dielectric is obtained, but lower level materials and contacts are degraded
Solution Approach 1:
The patent divides the transistor structure into upper and lower levels with spatial separation. The gate electrode of the upper level transistor is positioned below the upper semiconducting layer, allowing the gate dielectric to be formed and annealed without exposing the lower level transistor materials to high temperatures. This segmentation enables independent thermal processing of different levels.
Solution Approach 2:
The patent employs a flipped gate configuration where the gate electrode extends from the lower face of the upper semiconducting layer downward, rather than the conventional position above the layer. This dimensional repositioning allows the gate dielectric formation zone to be separated from the lower level transistor structures, enabling high-temperature processing at the upper level without thermal damage to lower levels.
2Reliability
If thermal oxide gate dielectric is integrated for upper level transistors, then stable threshold voltage is achieved, but thermal budget exceeds 550°C
Solution Approach 1:
The patent performs the thermal oxide formation and annealing process on the upper level transistor gate dielectric before assembling the upper level structure onto the lower level transistor. By completing the high-temperature thermal budget requirements in advance, the subsequent assembly and lower level processing can proceed at lower temperatures, preventing thermal degradation of temperature-sensitive lower level materials.
3Reliability
If conventional interconnection structure is used to connect upper and lower level transistors, then electrical connection is achieved, but interconnection size and complexity increase
Solution Approach 1:
The patent merges the gate electrode of the upper level transistor with the interconnection structure. The gate electrode serves dual functions: controlling the upper level transistor channel and providing the vertical interconnection to the lower level transistor. This eliminates the need for separate via and contact structures, reducing interconnection complexity and improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of high-quality upper level transistors with reduced thermal impact on lower levels, improved inter-level connections, and enhanced thermal oxide gate dielectrics, maintaining stable threshold voltage over time while minimizing thermal budget and interconnection density.
Implementation Method 1
a thermal oxide layer (102) already present on the second semiconducting layer (110), this thermal oxide layer (102) being produced prior to the assembly and in particular by means of at least one annealing step at a temperature above 600° C.
Implementation Method 2
this thermal oxide layer (102) being produced prior to the assembly and in particular by means of at least one annealing step at a temperature above 600° C.
Implementation Method 3
the localized thinning includes the oxidation of an upper portion of said given zone at a temperature below 500° C.
Data Source
AI summary
An integrated circuit is provided with several superimposed levels of transistors, the circuit including an upper level provided with transistors having a rear gate electrode laid out on a first semiconducting layer, and a second semiconducting layer, a first transistor among the transistors of the upper level being provided with a contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer that is opposite to the rear face.