Flipped Staircase Interconnect Layout for Higher BEOL Density
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Solution Overview
Problem
The challenge in integrated circuit (IC) fabrication is to optimize the density and arrangement of interconnect structures in the back-end of line (BEOL) stage, where building directly over the front-end of line (FEOL) has disadvantages, necessitating innovative interconnect designs to enhance performance and capacity.
Innovation Solution
The implementation of flipped staircase interconnect structures, where conductive lines are stacked with their first ends aligned and lengths gradually decreasing closer to the support structure, offering a unique arrangement that improves interconnect density and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional staircase interconnect structures are used, then interconnect density is improved, but manufacturing complexity and alignment precision requirements increase
Solution Approach 1:
The patent inverts the traditional staircase interconnect configuration by flipping it 180 degrees. Instead of having the wider portion of conductive lines at the top, the flipped staircase structure has the wider portion at the bottom, closer to the active devices. This inversion maintains high interconnect density while simplifying the alignment process during fabrication, as the narrower portions are positioned where precise alignment is less critical.
Solution Approach 2:
The flipped staircase interconnect structure employs asymmetric geometry where conductive lines of different widths are stacked at offset positions. The structure features a first conductive line with a first width and a second conductive line with a second width greater than the first width, arranged in a stepped configuration. This asymmetric design optimizes signal routing and reduces interference while maintaining manufacturability.
2Quantity of substance
If feature scaling is continued to increase device density, then capacity increases, but interconnect performance optimization becomes increasingly significant and difficult
Solution Approach 1:
The patent transitions from two-dimensional planar interconnect layouts to three-dimensional stacked configurations. By arranging conductive lines in vertical stacks with different widths at different heights, the flipped staircase structure utilizes the third dimension to increase interconnect density without further shrinking feature sizes, thereby maintaining performance as devices scale to smaller dimensions.
Solution Approach 2:
The flipped staircase interconnect structure implements a nested arrangement where multiple conductive lines are stacked vertically, with each layer containing conductive lines of appropriate widths for specific signal routing needs. This nested configuration allows multiple interconnect functions to be integrated within a compact vertical space, reducing the complexity of routing signals in scaled-down devices.
Data Source
AI summary
An example IC device includes a support structure; a device layer over or at least partially in the support structure, the device layer comprising transistors; and an interconnect layer. The device layer is between the support structure and the interconnect layer, and the interconnect layer includes a first conductive line and a second conductive line stacked above the first conductive line. A first end of the first conductive line is substantially aligned with a first end of the second conductive line along a plane perpendicular to the substrate, and a second end of the first conductive line is closer to the plane than a second end of the second conductive line. Such an arrangement of conductive lines may be referred to as “flipped staircase.”