Flipped Transistor Pair Assembly for Low-Inductance Power Electronics
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Solution Overview
Problem
Existing power electronics assemblies face challenges in minimizing size and reducing parasitic inductance and thermal effects due to the separate placement of power electronic devices, gate drive devices, and capacitors, which impacts performance and efficiency.
Innovation Solution
A compact power electronics assembly design featuring transistor pairs with one transistor flipped relative to the other, with lead frames and output lead frames arranged in a common plane to reduce size and parasitic inductance, and incorporating insulating layers for thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If power electronic devices, gate drive devices, and capacitors are placed separately in conventional semiconductor packages, then each component can be individually optimized, but the overall assembly size increases and parasitic inductance is generated
Solution Approach 1:
The patent combines power electronic devices, gate drive devices, and capacitors into a single integrated semiconductor package with a common substrate. Multiple transistor pairs are mounted on the same substrate with their associated lead frames interconnected, eliminating the need for separate packages and reducing overall assembly volume while minimizing parasitic inductance through integrated electrical connections.
Solution Approach 2:
The patent implements a nested structure where transistor pairs are integrated within the semiconductor package substrate, with lead frames interconnected in a compact arrangement. The flipped chip configuration allows transistors to be nested closely together, with source terminals connected to common lead frames, creating a compact hierarchical structure that reduces space while maintaining electrical performance.
2Reliability
If transistor pairs are arranged in a flipped configuration with common lead frames, then parasitic inductance is minimized and electrical performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor package into discrete transistor pairs, each with its own lead frame structure that can be independently fabricated and then interconnected. This segmentation allows for modular manufacturing where standard fabrication processes can be applied to each transistor pair, reducing overall manufacturing complexity despite the integrated design.
Solution Approach 2:
The patent employs a flipped chip configuration where transistors are mounted with their active surfaces facing opposite directions, and source terminals are connected to common lead frames through the substrate. This inverted arrangement optimizes electrical performance by minimizing current path inductance while allowing for standardized bonding processes that simplify manufacturing.
3Volume of moving object
If multiple transistor pairs are integrated in a common plane on a single substrate, then assembly size is reduced, but thermal management becomes more challenging
Solution Approach 1:
The patent introduces a common substrate as an intermediary thermal management structure that conducts heat away from multiple transistor pairs simultaneously. The substrate serves as a heat spreader with integrated thermal pathways, allowing compact arrangement of transistor pairs while maintaining effective heat dissipation through the common base structure.
Data Source
AI summary
Methods, apparatuses and systems provide for technology that includes a transistor assembly for a power electronics apparatus having a plurality of transistor pairs arranged in a common plane, where for each pair of transistors one transistor is flipped relative to the other transistor. The technology further includes a first lead frame arranged parallel to and electrically coupled to the first transistor in each transistor pair, a second lead frame coplanar to the first lead frame and arranged parallel to and electrically coupled to the second transistor in each transistor pair, and a plurality of output lead frames arranged coplanar to each other, where each respective output lead frame is arranged parallel to and electrically coupled to a respective one pair of the plurality of transistor pairs.